基于FPGA的DDFS信号发生器设计  

Design of DDFS Signal Generator Based on FPGA

作　　者：杨敏[1] 王利[1] 张金时 裴水源 罗浩 YANG Min;WANG Li;ZHANG Jinshi;PEI Shuiyuan;LUO Hao(School of Mechanical Engineering,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学机电工程学院,山西太原030051

出　　处：《自动化仪表》2019年第2期95-97,102,共4页Process Automation Instrumentation

摘　　要：基于直接数字频率合成(DDFS)的基本原理,设计了基于现场可编程门阵列(FPGA)的DDFS信号发生器。给出了硬件描述语言Verilog HDL编程实现方法。信号发生器所需要的波形数据由Matlab生成,再通过Quartus将波形数据转换成. mif文件;通过调用ROM IP核的方式,将. mif文件中的波形数据导入FPGA的RAM中。采用JTAG将整个启动程序配置到EPCS flash中。上电时,FPGA从EPCS获取配置程序,使得该信号发生器可以脱离计算机独立工作。通过增加按键进行波形类型的选择,并同时调节波形频率与相位。通过增加LCD来进行显示按键数据,以便与示波器观察到的数据进行对比。该信号发生器幅值范围为0～5 V,频率范围为1～100 kHz,波形可为正弦波、三角波、方波。仿真与实际测试结果表明,该信号发生器设计合理、准确性高、结构简单、使用方便。Based on the basic principle of Direct Digital Frequency Synthesis (DDFS),DDFS signal generator based on field programmable gate array (FPGA) is designed.The programming implementation method of hardware description language Verilog HDL is given.The waveform data needed by signal generator is generated by Matlab,and then converted into mif file by Quartus.The waveform data in mif file is imported into RAM of FPGA by calling ROM IP core.Then the whole startup program is configured into EPCS flash by JTAG.When power is on,the configuration program is acquired from EPCS by FPGA,to make the signal generator work independently without PC.To select the type of waveform,buttons are added,and the frequency and phase of waveform are adjusted at the same time.LCD is equipped to display button data,it is easy to compare with the data observed by the oscilloscope.The signal generator ranges in amplitude from 0 to 5V and frequency from 1Hz to 100KHz.The waveforms can be sine wave,triangle wave and square wave.The simulation and actual test results show that the design is reasonable,the signal generator features high accuracy,simple structure and convenient use.

关 键 词：直接数字频率合成 现场可编程门阵列 信号发生器 VERILOGHDL LCD DAC Matlab Flash 

分 类 号：TH86[机械工程—仪器科学与技术]