基于FPGA+SCV64架构的VME总线从模块开发  

Development of VME Bus Slave Module Based on FPGA+SCV64 Architecture

作　　者：白煊 罗运虎[1] 郑永龙[2] 周勇军[2] BAI Xuan;LUO Yun-hu;ZHENG Yong-long;ZHOU Yong-jun(College of Automation Engineering,Nanjing University of Aeronautics & Astronautics,Nanjing 210016,China;Aviation Equipment Monitoring and Control and Reverse Engineering Laboratory,No.5720 Factory of the PLA,Wuhu 241007,China)

机构地区：[1]南京航空航天大学自动化学院,江苏南京210016 [2]中国人民解放军第5720工厂安徽省航空设备测控与逆向工程实验室,安徽芜湖241007

出　　处：《测控技术》2019年第2期108-112,共5页Measurement & Control Technology

摘　　要：为满足新机VME总线模块电路板深修的需要,基于VME总线接口协议芯片SCV64,开发了具有接收VME总线信号读写操作功能的从模块。该从模块可实现对机上VME总线模块通信能力检测。给出其硬件架构与各部分电路设计,基于Verilog语言对其读写功能进行软件开发,并给出其硬件设计与软件开发过程中需要注意的问题。对从模块功能进行测试,测试结果表明其功能有效。研制的VME总线从模块能够为后续VME总线模块的测试与维修提供技术支撑。In order to meet the needs of the deep repair of the VME bus module circuit board on the new aircraft,based on the VME bus interface protocol chip SCV64,a slave module that accepts the VME bus signal read/write operation function has been developed.The slave module can detect the communication capability of the on-board VME bus module.The hardware architecture and various circuit designs are given.The software is developed based on Verilog HDL.The issues that need to be addressed during the hardware design and software development process are described.The slave module was tested and the results showed that its function was available.The developed VME bus slave module can provide technical support for testing and repairing VME bus modules in subsequent new models.

关 键 词：VME总线 FPGA SCV64 数据通信 

分 类 号：TP336[自动化与计算机技术—计算机系统结构] V243[自动化与计算机技术—计算机科学与技术]