一种多线程阵列众核处理器的二级Cache划分机制  

A L2 cache partitioning mechanism for multithreaded array-based many-core processors

作　　者：陈逸飞 朱蕾[1] 李宏亮[1] CHEN Yi-fei;ZHU Lei;LI Hong-liang(Jiangnan Institute of Computing Technology,Wuxi 214083,China)

机构地区：[1]江南计算技术研究所,江苏无锡214083

出　　处：《计算机工程与科学》2019年第3期400-408,共9页Computer Engineering & Science

摘　　要：阵列众核处理器由于其较高的计算性能和能效比已经广泛应用于高性能计算领域。而要构建未来高性能计算系统处理器必须解决严峻的"访存墙"挑战以及核心协同问题。通常的阵列处理器,其核心多采用单线程结构,以减少开销,但是对访存提出了较高的要求。引入硬件同时多线程技术,针对实验中单核心多线程二级Cache利用率较低的问题,提出了一种共享二级Cache划分机制。经实验模拟,通过上述优化的共享二级Cache划分机制,二级指令Cache失效率下降18.59%,数据Cache失效率下降6.60%,整体CPI性能提升达到10.1%。Because of its high computational performance and energy efficiency ratio, array-based many-core processors have been widely used in the high performance computing field. To build future high performance computing systems, processor must solve the severe challenge of ‘memory wall’ and core synergy problem. In a typical array-based many-core processor, the core adopts the single-threaded structure to reduce overhead. However, the demand for memory access is higher. We introduce the hardware simultaneous multithreading technology into the single core structure. Aiming at the problem that the utilization rate of the single-core multi-threaded L2 cache is significantly low, we present a L2 cache partitioning mechanism (thread-based cache partitioning) for the array-based many-core processor. Experimental results demonstrate that, based on the L2 cache partition mechanism, the miss rate of the L2 instruction cache is decreased by 18.59%, the miss rate of the L2 data cache is decreased by 6.60% and the CPI performance is increased by 10.1%.

关 键 词：阵列众核处理器 同时多线程 共享二级Cache划分机制 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]