一种适合FPGA实现的低错误平层比特翻转算法  

An Improved Weighted Bit-flipping Decoding Algorithm Suitable for the FPGA Realization

作　　者：马克祥 MA Ke-xiang(China Academy of Electronics and Information Technology,Beijing 100041,China)

机构地区：[1]中国电子科学研究院,北京100041

出　　处：《中国电子科学研究院学报》2019年第2期218-220,共3页Journal of China Academy of Electronics and Information Technology

摘　　要：本文提出一种改进加权比特翻转算法用于解决传统加权比特翻转算法FPGA实现时出现的性能恶化现象。仿真实验表明,加权比特翻转算法译码过程中出现的"伪零值"现象,是造成加权比特翻转算法利用FPGA平台实现时出现性能恶化的主要原因。本文算法通过修正校验节点品质因素值解决"伪零值"问题,进而使得改进算法利用FPGA平台实现时可以获得较好地仿真性能。实验结果验证了本文算法的有效性。In order to reduce the performance loss of the WBF decoder by the FPGA platform,we propose a improved WBF algorithm in this paper.The pseudo-zero phenomenon in the decoding process of the WBF algorithm results in the performance loss above,which is verified by the theoretical analysis and the simulation results.In the proposed algorithm,we resolve the pseudo-zero problem by modifying the check equation.Correspondingly,the proposed algorithm can obtain a good decoding performance when it is implemented by the FPGA platform.The validation of the proposed algorithm is verified by simulation.

关 键 词：LDPC码 错误平层 比特翻转 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]