应用于UWB系统的低硬件开销128点FFT处理器设计  

Design of Low Hardware-Cost 128-Point Fast Fourier Transform Processor for UWB System

作　　者：于建 赵炅柱 Yu Jian;Cho Kyungju(Department of Physics and Electronic Engineering,Hebei Normal University for Nationalities,Chengde,067000,China;Wonkwang University,Iksan,54538,South Korea)

机构地区：[1]河北民族师范学院物理与电子工程系,承德067000 [2]韩国圆光大学,益山54538

出　　处：《数据采集与处理》2019年第2期358-366,共9页Journal of Data Acquisition and Processing

基　　金：河北民族师范学院科研课题(PT201507)资助项目

摘　　要：快速傅里叶变换(Fast Fourier transform,FFT)处理器是数字信号处理领域的核心单元。本文针对超宽带(Ultra wideband,UWB)系统提出了一种低硬件开销的128点FFT处理器设计方案。此方案在算法上采用了混合基-24-23算法,硬件实现上采用了单路延迟负反馈(Single delay feedback,SDF)流水线架构,在处理复数乘法运算上,提出一种新型串接正则有符号数(Canonical signed digit,CSD)常数乘法器替代常用布斯乘法器对旋转因子W1i28的复数乘法运算进行实现,大幅降低了FFT处理器消耗的硬件资源。本文设计基于QUARTUS PRIME平台进行开发,并搭配Cyclone 10 LP系列器件,编译报告显示本文方案对比于其他已存在的方案,具有最低的硬件开销和功耗。Fast Fourier transform(FFT)is a key block in the field of digital signal processing(DSP).A low hardware-cost 128-point FFT for UWB system is presented in this paper.Mixed radix-24-23 algorithm is adopted,and single-path delay feedback(SDF)architecture is used for hardware implementation.A novel cascade canonical signed digit(CSD)multiplier is proposed for the complex multiplication of W128^i instead of the common booth multiplier,which can significantly reduce the hardware-cost.Based on QUARTUS PRIME tool with Cyclone 10 LP,the proposed scheme is developed,and the compilation report shows that the proposed scheme has the least hardware-cost and power consumption compared with the existing schemes.

关 键 词：傅里叶变换 混合基算法 CSD常数乘法器 布斯乘法器 流水线架构 

分 类 号：TN47[电子电信—微电子学与固体电子学]