基于改进的Quinn测频算法及其FPGA实现  

Frequency measurement algorithm based on improved Quinn algorithm and its FPGA implementation

作　　者：周胜文 詹磊[1] 廖春兰 马凡 刘平原 董晖 ZHOU Shengwen;ZHAN Lei;LIAO Chunlan;MA Fan;LIU Pingyuan;DONG Hui(Beijing Research Institute of Telemetry,China Aerospace Electronic Technology Research Institute,Beijing 100076,China;Telecommunication Technology Laboratory,China Academy of Information and Communications Technology,Beijing 100191,China)

机构地区：[1]中国航天电子技术研究院北京遥测技术研究所,北京100094 [2]中国信息通信研究院泰尔终端实验室,北京100191

出　　处：《太赫兹科学与电子信息学报》2019年第2期243-247,共5页Journal of Terahertz Science and Electronic Information Technology

摘　　要：在分析Quinn算法性能的基础上,提出一种改进的Quinn测频算法,并对该算法的原理和FPGA实现步骤进行详细说明。仿真结果表明:在低信噪比条件下新算法的估计性能不随被估计信号的频率分布而产生波动,在整个频段内估计均方根误差(RMSE)接近克拉美-罗下界(CRLB)。为了减少测频时间,新算法在FPGA平台实现时采用初始频偏的多项式函数构造频率估计值。实测结果表明新方法测频精确度高,测频时间短,可以用于快速测频场合。An improved Quinn algorithm is proposed based on analyzing the performance of Quinn algorithm. The principle and Field Programmable Gate Array(FPGA) implementation steps of the new algorithm are described in detail. The simulation results indicate that the performance of improved Quinn algorithm does not fluctuate with the distribution of signal frequency, and its Root Mean Square Error(RMSE) approaches to Cramer-Rao Lower Bound(CRLB) throughout the whole frequency range. In order to decrease the latency of frequency measurement, polynomial function of frequency deviation estimator is utilized to implement improved algorithm on FPGA. The experiment results demonstrate the new algorithm with high accuracy and less latency is suitable for fast frequency measurement.

关 键 词：频率估计 Quinn算法 克拉美-罗下界 现场可编程门阵列 

分 类 号：TN974[电子电信—信号与信息处理]