基于FPGA的高可靠EDAC系统设计  

Design of high reliability EDAC system based on FPGA

作　　者：于善鹏 占丰 姜连祥 Yu Shanpeng;Zhan Feng;Jiang Lianxiang(Shandong Institute of Space Electronic Technology, Yantai 264000, China)

机构地区：[1]山东航天电子技术研究所,山东烟台264000

出　　处：《质量与可靠性》2019年第2期29-33,共5页Quality and Reliability

摘　　要：为减少单粒子效应对存储器造成的数据错误影响,目前卫星上多采用汉明码编码方式实现的错误检测与纠正(EDAC)系统进行数据保护。为减少单粒子翻转造成的影响,利用现场可编程门阵列(FPGA)将三模冗余(TMR)与(16, 8)准循环码2种技术相结合,能够纠正单个存储器中的多位错误。通过4个FPGA实现的两级三模冗余系统,解决表决器模块单点失效的问题,对存储器中的数据进行保护,并通过仿真验证和可靠性分析证明系统的高可靠性。In order to reduce the impact of single event effect on data errors caused by memory,Hamming code coding are used for most of the EDAC systems implemented to protect data on the satellite at present. In order to reduce the impact of single event upsets, the combination of TMR and quasi-cyclic code(16, 8) in FPGA can correct multiple bit errors in a single memory. The two-level three modular redundant system implemented by four FPGA is used to solve the problem of single point failure of voting module, to protect data in memory and to prove the high reliability of the system through simulation and reliability analysis.

关 键 词：单粒子多位翻转 TMR (16  8)准循环码 高可靠性 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN791[自动化与计算机技术—计算机科学与技术]