dPMR接收机定时估计算法及FPGA实现  

A timing estimation algorithm for dPMR receiver based on FPGA and its implementation

作　　者：朱子文 张涛 关汉兴 Zhu Ziwen;Zhang Tao;Guan Hanxing(Engineering Research Center of Metallurgical Automation and Measurement Technology,Wuhan University of Science and Technology,Wuhan 430081,China;Yangtze Optical Fibre and Cable Joint Stock Limited Company,Wuhan 430000,China)

机构地区：[1]武汉科技大学冶金自动化与检测技术教育部工程研究中心,湖北武汉430081 [2]长飞光纤光缆有限公司,湖北武汉430000

出　　处：《电子技术应用》2019年第5期27-30,共4页Application of Electronic Technique

基　　金：国家自然科学基金(61501337)

摘　　要：符号定时同步的准确度对数字通信系统解调性能有极大影响,dPMR通信系统要求接收机的符号同步具有快速捕获和良好跟踪性能的特点。针对该要求,提出一种定时估计算法。该算法结合前导码定时算法和数字平方滤波算法的优点,首先捕捉突发信息的前导码,使用前导码定时算法实现高精度快速定时估计,之后以384个符号为间隔,使用数字平方滤波算法实现定时估计的跟踪校正。同时提出一种结构简单的FPGA实现方案,相对于经典的同步波形匹配滤波定时算法,不仅提升了接收机的解调性能且节约了硬件资源。The accuracy of symbol timing synchronization has a great impact on the demodulation performance of digital communication systems. The dPMR communication system requires the symbol synchronization of the receiver to have fast acquisition and good tracking performance. A timing estimation algorithm is proposed for this requirement. The algorithm combines the advantages of preamble timing algorithm and digital square filtering algorithm. Firstly, when the preamble of the burst information is captured, the preamble timing algorithm is used to implement high-precision fast timing estimation. Then, a digital square filtering algorithm is used to implement tracking correction for timing estimation at intervals of 384 symbols. At the same time, a simple FPGA implementation scheme is proposed. Compared with the classical matching filter timing algorithm based on synchronous waveform, it not only improves the demodulation performance of the receiver but also saves hardware resources.

关 键 词：定时估计 快速捕捉 定时跟踪 现场可编程门阵列 

分 类 号：TN929.5[电子电信—通信与信息系统]