UM-BUS总线测试系统中PCIe的设计与实现  

Design and implementation of PCIe on UM-BUS test system

作　　者：孙丰霞 张伟功[1,2,3] 周继芹 王莹[1] Sun Fengxia;Zhang Weigong;Zhou Jiqin;Wang Ying(School of Information Engineering,Capital Normal University,Beijing 100048,China;Beijing Advanced Innovation Center for Image Technology,Capital Normal University,Beijing 100048,China;Beijing Engineering Research Center of High Reliable Embedded System,Capital Normal University,Beijing 100048,China)

机构地区：[1]首都师范大学信息工程学院,北京100048 [2]首都师范大学北京成像技术高精尖创新中心,北京100048 [3]首都师范大学高可靠嵌入式系统技术北京市工程技术研究中心,北京100048

出　　处：《电子技术应用》2019年第5期61-65,共5页Application of Electronic Technique

基　　金：国家自然科学基金项目(61741211)

摘　　要：UM-BUS总线单通道理论带宽可达200 Mb/s,采用16通道并发传输时,理论带宽可达400 MB/s,其测试系统需要在数据采集终端与PC之间建立不低于此带宽的通信通道。PCIe1.1采用4通道传输时理论带宽可达1 GB/s,满足了UM-BUS总线测试系统的传输带宽需求,由此设计实现了UM-BUS总线测试系统的PCIe1.1 x4链路通道的应用方案,给出了基于FPGA的PCIe总线的BMD传输方案。测试结果表明,该方案实际传输速度可达550 MB/s,满足UM-BUS总线测试系统的带宽需求。The single channel theoretical bandwidth of the UM-BUS can be up to 200 Mb/s. When 16 channels are used for concurrent transmission, the theoretical bandwidth can be up to 400 MB/s. So the test system needs to establish a communication channel of no less than this bandwidth between the data acquisition terminal and PC. In PCIe1. 1, the theoretical bandwidth of the four channel transmission is up to 1 GB/s, which meets the transmission requirements of the UM-BUS test system. Thus, this pa-per realizes the application scheme of PCIe1. 1 x4 link channel of UM-BUS bus test system, and gives the BMD transmission scheme of PCIe bus based on FPGA. The test result shows that the actual transmission speed of the scheme can reach 550 MB/s,which satisfies the bandwidth requirements of the UM-BUS bus test system.

关 键 词：UM-BUS总线 总线测试系统 PCIe总线 BMD 数据通信 

分 类 号：TN919[电子电信—通信与信息系统] TP391[电子电信—信息与通信工程]