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作 者:谢天娇 李波[1] 杨懋[1] 闫中江[1] XIE TianJiao;LI Bo;YANG Mao;YAN Zhongjiang(School of Electronics and Information, Northwestern Polytechnical University, Xi′an 710072, China;China Academy of Space Technology(Xi′an), Xi′an 710100, China)
机构地区:[1]西北工业大学电子信息学院,陕西西安710072 [2]中国空间技术研究院西安分院,陕西西安710100
出 处:《西北工业大学学报》2019年第2期299-307,共9页Journal of Northwestern Polytechnical University
基 金:国家自然科学基金(61501373;61771390;61771392;61271279);国家科技重大专项(2016ZX03001018-004);中央高校基本科研业务费项目(3102017ZY018)资助
摘 要:提出了一种基于现场可编码门阵列(field programmable gate Array,FPGA)的高速码率兼容第二代数字电视广播(digital video broadcast:second generation,DVB-S2)标准的低密度奇偶校验码(low density parity check codes,LDPC)译码器架构,通过对DVB-S2的LDPC码校验矩阵进行初等变换得到新的矩阵,由准循环(quasi-cyclic,QC)子矩阵和行变换下三角双对角子矩阵(transformation of staircase lower triangular,TST)组成。提出的译码器架构QC部分利用现阶段研究最多的准循环QC-LDPC译码器技术,而对于TST部分,只需兼容QC矩阵部分,提出的架构可以按照QC的架构而动态地改变TST的并行路数,而且分开存储TST与QC的更新消息,保证了码率兼容。基于Xilinx XC7VX485T FPGA的验证结果表明,5种码率兼容的DVB-S2 LDPC译码器,可到达时钟频率250 MHz,最大迭代次数20次,对应的译码器最大吞吐量为2.5 Gbit/s。A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.
关 键 词:高速LDPC译码器 码率兼容 DVB-S2标准 FPGA
分 类 号:TN92[电子电信—通信与信息系统]
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