带输入缓冲电路的12位200兆流水线模数转换器  

A 12 bit 200 Msps Pipelined ADC with Input Buffer

作　　者：林海军[1] 张泽旺[1,2] 陈路遥 梁波 邓文涛 LIN Haijun;ZHANG Zewang;CHEN Luyao;LIANG Bo;DENG Wentao(Xiamen University of Technology,Fujian,Xiamen,361024;College of Information Science and Electronic Engineering Zhejiang University,Hangzhou,310058)

机构地区：[1]厦门理工学院,福建厦门361024 [2]浙江大学信息与电子工程学院,杭州310058

出　　处：《固体电子学研究与进展》2019年第2期131-137,共7页Research & Progress of SSE

基　　金：福建省教育厅中青年教师教育科研项目(JAT160324;JT180458)

摘　　要：在12 bit 200 M采样率的模数转换电路(ADC)中实现了片内CMOS输入缓冲电路,输入缓冲电路采用源极跟随器电路构架。通过分析源极跟随器的非线性特点,在输入缓冲电路中加入高通滤波电路、复制电容电路等方式,有效提高了输入缓冲电路的线性度。将该输入缓冲电路用于无数字校准的12 bit 200 M采样率的流水线型模数转换电路(ADC)中,用台积电0.18μm CMOS工艺条件下流片验证,当采样时钟为200 MHz、输入信号频率为10 MHz、振幅为1.4 V_(pp)时其失真噪声比(SNDR)为63.5 dB,无杂散动态范围(SFDR)为78.6 dBc,ADC总体功耗为500 mW。A 12 bit 200 Msps pipeline ADC with on chip CMOS input buffer was realized. Source follower circuit architecture was adopted in the input buffer circuit. By analyzing nonlinearity of source follower, and adding high pass filter, replicating capacitance to the input buffer circuit, the linearity of input buffer was effectively improved. The input buffer was implemented in 12 bit 200 Msps pipelined ADC without digital calibration and fabricated by TSMC 0.18 μm CMOS technology. The ADC achieves the spurious free dynamic range(SFDR) of 78.6 dB, the signal to noise and distortion ratio(SNDR) of 63.5 dB with input signal frequency of 10 MHz, input signal amplitude of 1.4 Vpp and sampling frequency of 200 MHz. The whole ADC consumes 500 mW of power.

关 键 词：输入缓冲电路 模数转换 高线性度 

分 类 号：TN432[电子电信—微电子学与固体电子学]