雷达接收机综合测试系统设计  

Design of Radar Receiver Integrated Test System

作　　者：钱程 钱叶旺[1] 许亚男[1] QIAN Cheng;QIAN Ye-wang;XU Ya-nan(School of Mechanical and Electrical Engineering,Chizhou University,Chizhou 247100,China)

机构地区：[1]池州学院机电工程学院,安徽池州247100

出　　处：《通信电源技术》2019年第5期68-70,共3页Telecom Power Technology

基　　金：2016年池州学院科研项目"基于AES加密算法的安全芯片研究"(2016ZR004);安徽省高校自然科学重点项目"OFDM-MIMO雷达对低空高速目标探测关键技术研究"(KJ2016A515);池州学院校企合作实践基地项目(2017SJJD105);2017年池州学院科研自然重点项目"基于Contourlet的图像处理方法研究"(2017ZRZ007)

摘　　要：针对雷达接收机测试过程高速、实时及数据量大的特点,设计了一种高性能雷达接收机综合测试系统。该系统由真实仪器组和专用虚拟仪器组成,基于FPGA设计的高速数据采集卡通过光纤接口采集雷达接收机数据,并通过CPCI总线将数据送至工控机,由专用虚拟仪器分析软件对雷达数据进行分析测量,最终完成对接收机工作参数、性能的快速测试。详细介绍了雷达接收机综合测试系统的组成、高速数据采集卡等硬件设计以及专用虚拟仪器分析软件的设计。In view of the characteristics of high speed,real time and large amount of data in the test process of radar receiver,designing a high performance radar receiver comprehensive test system. The system is composed of real instrument group and the special virtual instrument,based on the FPGA design of high-speed data acquisition card through the optical fiber interface data acquisition radar receiver,the data sent to the industrial control,and through the cpci-bus by special virtual instrument analysis software to analyze measured radar data,finally complete the performance of the receiver working parameters,quick test. The composition of radar receiver comprehensive test system,the hardware design of high-speed data acquisition card and the design of special virtual instrument analysis software are introduced in detail.

关 键 词：雷达接收机 虚拟仪器分析软件 高速数据采集卡 FPGA 

分 类 号：TN957.5[电子电信—信号与信息处理]