一种用于时延积分CMOS图像传感器的10 bit全差分双斜坡模数转换器  

A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors

作　　者：张鹤玖 余宁梅[1] 吕楠 刘尕 ZHANG Hejiu;YU Ningmei;LU Nan;LIU Ga(School of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, China;School of Information Technology and Equipment Engineering, Xi’an University of Technology, Xi’an 710082, China)

机构地区：[1]西安理工大学自动化与信息工程学院,西安710048 [2]西安理工大学信息技术与装备工程学院,西安710082

出　　处：《电子与信息学报》2019年第6期1466-1471,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61771388,61801378);西安市科技计划项目(201805037YD15CG21(11))~~

摘　　要：为了满足时间延时积分(TDI)CMOS图像传感器转换全差分信号的需要,同时符合列并行电路列宽的限制,该文提出并实现了一种10 bit全差分双斜坡模数转换器(ADC)。在列并行单斜坡ADC的基础上,采用2个电容的上极板对差分输入进行采样,电容下极板接2个斜坡输出完成量化。基于电流舵结构的斜坡发生器同时产生上升和下降斜坡,2个斜坡的台阶电压大小相等。该电路使用SMIC 0.18μm CMOS工艺设计实现,ADC以19.49 k S/s的采样频率对1.32 kHz的输入进行采样,仿真得到无杂散动态范围和有效位数分别为87.92 dB和9.84 bit。测试显示该ADC的微分非线性误差和积分非线性误差分别为–0.7/+0.6 LSB和–2.6/+2.1 LSB。A 10 bit fully differential dual slope Analog-to-Digital Converter (ADC) for Time Delay Integration (TDI) CMOS image sensors is realized based on column-parallel single-slope ADC. Top plates of the two capacitors are used for sampling differential inputs, and the bottom plates are connected to ramp generator for conversion. Current steering is used to generate the rising and falling ramp with the same step voltage simultaneously. The proposed ADC is fabricated in SMIC 0.18 μm CMOS process. Simulated spurious free dynamic range and effective number of bits are 87.92 dB and 9.84 bit with the input frequency of 1.32 kHz at 19.49 kS/s sampling rate, respectively. Measured results show that the ADC has a differential nonlinearity of –0.7/+0.6 LSB and integral nonlinearity of –2.6/+2.1 LSB.

关 键 词：列并行模数转换器 全差分输入 电流舵斜坡发生器 比较器 

分 类 号：TP335.1[自动化与计算机技术—计算机系统结构] TN432[自动化与计算机技术—计算机科学与技术]