面向机器学习的高性能SIMT处理器cache的设计与实现  

DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE SIMT PROCESSOR CACHE FOR MACHINE LEARNING

作　　者：许晓燕 李涛 孙哲 邢立冬 Xu Xiaoyan;Li Tao;Sun Zhe;Xing Lidong(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,Shaanxi,China)

机构地区：[1]西安邮电大学电子工程学院

出　　处：《计算机应用与软件》2019年第7期282-286,333,共6页Computer Applications and Software

基　　金：陕西省重点研发计划项目(2017ZDXM-GY-005);西安市科技局项目(201805040YD18CG24(5))

摘　　要：为了满足机器学习中大数据、并行计算及降低处理器与主存之间的差距等要求,设计基于自主研发的SIMT处理器的流水线cache结构。依据局部性原理与LRU替换算法相结合设计专用的伪LRU替换算法,与通用的轮询、LFU、LRU替换算法共同完成cache替换算法的可配置要求,实现处理器与主存之间的快速交互。采用Xilinx公司virtex ultrascale系列的xcvu440-flga2892-2-e FPGA芯片对设计进行综合。结果表明该结构指令cache最大时延为2.923 ns,数据cache最大时延为3.258 ns,满足SIMT处理器性能要求。In order to meet the requirements of big data,parallel computing and reduce the gap between processor and main memory in machine learning,we designed a pipeline cache structure based on self-developed SIMT processor. It was designed according to the principle of locality and LRU replacement algorithm. The dedicated pseudo LRU replacement algorithm,together with the general Round Robin,LFU,and LRU replacement algorithms,completed the configurable requirements of the cache replacement algorithm to achieve fast interaction between the processor and the main memory. The design was integrated with the xcvu440-flga2892-2-e FPGA chip of Xilinx virtex ultrascale series. The results show that the maximum latency of the structure instruction cache is 2.923 ns,and the maximum delay of the data cache is 3.258 ns,which satisfies the performance requirements of SIMT processor.

关 键 词：SIMT处理器 流水线cache结构 替换算法 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]