一种针对分组密码的抗能量攻击电路设计  

An anti-power attack circuit design for block cipher

作　　者：严迎建[1] 郑震 Yan Yingjian;Zheng Zhen(3rd College,Information Engineering University,Zhengzhou 450001,China)

机构地区：[1]信息工程大学三院

出　　处：《电子技术应用》2019年第8期109-112,117,共5页Application of Electronic Technique

摘　　要：为提高分组密码算法电路的抗能量攻击能力,参考掩码技术的思想,基于取反的基本操作提出了反向交错的概念,对反向交错的关键性质进行了证明,以此为依据设计了一种反向交错的电路结构,并通过加入一级寄存器的方式打乱时序对齐,得到了优化的电路结构,通过功耗随机化的方法提升了算法的抗能量攻击能力。最后将该结构应用到AES-128算法电路中并进行了加解密功能、防护功能和运算性能三方面的验证,结果表明本文设计的电路结构能正确进行加解密,且具有较好的防护效果和运算性能。In order to improve the anti-power attack capability of the block cipher algorithm circuit, the concept of reverse interleaving is proposed based on the idea of masking technology. The key properties of reverse staggering are proved. An inverted interleaved circuit structure is designed, the timing alignment is disturbed by adding a first-level register, and an optimized circuit structure is obtained. The anti-energy attack capability of the algorithm is improved by power randomization. Finally, the structure is applied to the AES-128 algorithm circuit and verified by encryption, decryption, protection and computational performance. The results show that the circuit structure designed in this paper can be correctly encrypted and decrypted, and has better protection effect and computing performance.

关 键 词：分组密码 抗能量攻击 掩码技术 反向交错 功耗随机化 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]