基于FPGA的高速可信计算平台的设计与实现  

Design and implementation of high-speed trusted computing platform based on FPGA

作　　者：姚蕊[1] 赵漫菲[1] 王仁 王永让 徐浩然 YAO Rui;ZHAO Man-fei;WANG Ren;WANG Yong-rang;XU Hao-ran(Institute 706,Second Academy of China Aerospace Science and Industry Corporation,Beijing 100854,China;Field Artillery and Air Defense Artillery Research Insitute of Army Research Academy,Beijing 100012,China)

机构地区：[1]中国航天科工集团第二研究院706所,北京100854 [2]陆军研究院炮兵防空兵研究所,北京100012

出　　处：《计算机工程与设计》2019年第8期2151-2160,共10页Computer Engineering and Design

摘　　要：为解决当前可信计算平台数据交换速率慢的缺点,提出基于高速串行计算机扩展总线标准即PCIe(peripheral component interconnect express,PCI Express)总线协议,使用Altera公司的CycloneIIII系列的现场可编程门阵列(field programmable gate array,FPGA)实现主机与TCM密码设备之间的高速数据传输硬件平台。基于双缓冲区高速乒乓切换和单缓冲区高速流水读写的硬件优化机制以及驱动层的直接内存存取(direct memory access,DMA)+中断机制和共享内存的软件优化机制,设计并实现一套完整的高性能可信计算平台,有效提高了可信计算平台的通信性能。To improve the slow data exchange rate of the current trusted computing platform,a complete set of high performance trusted computing platform was designed and implemented.Based on PCI Express bus protocol,the high speed data transmission access of the platform between the host and TCM device was realized by using FPGA of Altera company ’s CycloneIIII series.The whole optimization mechanism of the platform was made up of the hardware optimization methods and the software optimization methods,which effectively improved the communication performance of the trusted computing platform.Concretely,the hardware optimization mechanism consisted of the dual buffer high speed table tennis handover method and high speed water reading and writing method in single buffer zone.The software optimization mechanism was composed of DMA+ interrupt and shared memory on the driver layer.

关 键 词：PCIe总线 现场可编程门阵列 高速可信计算平台 乒乓操作 流水读写 直接内存存取 共享内存 

分 类 号：TP319[自动化与计算机技术—计算机软件与理论]