抑制电网谐波和直流电压的新型锁相环研究  

Research on a novel phase-locked loop for suppressing grid harmonic and DC voltage

作　　者：童涛 张新燕[1] 张家军 高亮 Tong Tao;Zhang Xinyan;Zhang Jiajun;Gao Liang(School of Electrical Engineering,Xinjiang University,Urumqi 830047,China)

机构地区：[1]新疆大学电气工程学院

出　　处：《电测与仪表》2019年第16期79-84,共6页Electrical Measurement & Instrumentation

基　　金：国家自然科学基金资助项目(51667018)

摘　　要：针对在电网电压含多次谐波和直流电压时解耦双同步参考坐标系锁相环(DDSRF-PLL)对频率和相位锁定存在较大偏差,提出一种新型锁相环,该锁相环在dq信号正负序解耦前添加新型正交信号发生器(SOGI-QSG)来滤除谐波和直流电压,为解耦双同步参考坐标系锁相环提供稳定的αβ信号,从而提高锁相环抑制谐波和直流电压能力。对该锁相环Matlab/Simulink仿真研究并与解耦双同步参考坐标系锁相环和添加传统正交信号发生器的解耦双同步参考坐标系锁相环进行对比,验证了该锁相环在电网电压含多次谐波和直流电压时能够滤除电压谐波和直流电压,锁频锁相效果较好,有效提高了系统稳定性和可靠性。When the grid voltage contains multiple harmonics and DC voltages,the decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL) has a large deviation from the frequency and phase locking of the grid voltage.A novel PLL proposed in this paper adds a new type of orthogonal signal generator (SOGI-QSG) to filter out harmonics and DC voltage before decoupling the positive and negative sequence of dq signals,and provides DDSRF-PLL with a steady alpha beta signal,which improves the ability of the PLL to suppress harmonics and DC voltages.Matlab/Simulink simulation research of the PLL and comparison with DDSRF-PLL and DDSRF-PLL adding traditional orthogonal signal generator verify that the PLL can filter out the harmonics and DC voltage in the grid voltage containing multiple harmonics and DC voltage,and the effect of frequency and phase lock is better,which can effectively improve the stability and reliability of the system.

关 键 词：锁相环 多次谐波 直流电压 正交信号发生器 

分 类 号：TM933[电气工程—电力电子与电力传动]