基于子矩阵分裂技术的高速LDPC译码器设计与实现  

Design and implementation of high-speed LDPC decoder based on sub-matrix splitting technique

作　　者：张占义 朱金达[2] Zhang Zhanyi;Zhu Jinda(Hebei Jiaotong Vocational and Technical College, Shijiazhuang 050035, China;Hebei University of Science and Technology, Shijiazhuang 050018, China)

机构地区：[1]河北交通职业技术学院,石家庄050035 [2]河北科技大学,石家庄050018

出　　处：《电子测量与仪器学报》2019年第6期141-148,共8页Journal of Electronic Measurement and Instrumentation

基　　金：河北省自然科学基金(F2005000077);河北省重点研发计划(18214312D);河北省技术创新引导计划(17044313Z)资助项目

摘　　要：通过分析低密度奇偶校验(LDPC)码归一化最小和译码算法的特点,给出了LDPC码译码器整体结构和硬件实现的设计方案。通过分析与比较长码与短码的硬件实现参数,提出了一种在长码译码器两端分别增加串并、并串转换模块来提高译码速率以及能够提高译码并行度的译码校验矩阵的子矩阵分裂技术的设计思路。在具体的设计和实现中,详细介绍了译码器各模块的存储RAM与变量、校验节点更新处理模块的设计方案,同时还提出了迭代处理模块存储RAM的“空分”处理寻址方法。最后,测试结果表明,该译码器的稳定译码速率可达365 Mbps,从而实现了高速译码的设计要求,因此在卫星通信、5G移动通信等通信领域具有一定的应用前景。The hardware implementation of decoder of low density parity check( LDPC) code with high speed is presented,which is based on the use of the scaled min-sum decoding algorithm. With the comparison analysis of the implementation parameters between long code and short code,a method is proposed by adding the serial to parallel module and it is parallel to serial module at input and output ends of the decoder independently to improve the decoding speed for a long code. Then a sub-matrix splitting technique for the paritycheck matrix was introduced to improve the decoding parallelism. A new addressing method which is based on the space division multiplexing of the RAM of the iterative processing module is also proposed. Experiment results show that the stable decoding rate of the designed FPGA decoder is up to 365 Mbps,thus,having certain application prospects for some communication fields such as satellite communications,5G mobile communications,etc.

关 键 词：准循环LDPC码 最小和译码算法 高速译码器 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]