SM4加密算法可裁剪式结构设计与硬件实现  

Cuttable Structure Design and Hardware Implementation of SM4 Encryption Algorithm

作　　者：刘金峒 梁科[2] 王锦[2] 陈新伟[3] 徐华超[2] 李国峰[2] Liu Jintong;Liang Ke;Wang Jin;Chen Xinwei;Xu Huachao;Li Guofeng(College of Electrical and Control Engineering,North China Institute of Aerospace Engineering,Langfang 065000, China;Tianjin Key Laboratory of Optoelectronic Sensor and Sensing Network Technology,College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300071, China;Collaborative Innovation Center of IoT Industrialization and Intelligent Production,Minjiang University, Fuzhou 350000, China)

机构地区：[1]北华航天工业学院电子与控制工程学院,河北廊坊065000 [2]南开大学电子信息与光学工程学院,天津市光电传感器与传感网络技术重点实验室,天津300350 [3]闽江学院物联网产业化与智能生产协同创新中心,福建福州350121

出　　处：《南开大学学报（自然科学版）》2019年第4期41-45,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：闽江学院物联网产业化与智能生产协同创新中心开放基金(IIC1706)

摘　　要：SM4算法是国家密码管理局发布的一种主要应用于无线局域网产品中的分组加密算法.从硬件实现的角度对SM4算法原理进行分析,依次设计了循环迭代结构与全并行流水线结构,并在此基础上进一步优化,最终提出了一种更为灵活的部分并行可裁剪式结构.该结构可根据系统性能要求,对硬件电路结构进行裁剪,改善了循环迭代结构数据处理慢与全并行流水线结构逻辑资源消耗大的问题.最后通过硬件描述语言对以上结构完成行为级描述与功能仿真,并在Altera FPGA器件上进行了综合与数据分析.综合结果表明,可裁剪式结构在满足系统性能要求的基础上逻辑资源面积更小,功耗更低.SM4 algorithm is a packet encryption algorithm which is issued by the state encryption administration and majorly applied to WLAN products.The principle of SM4 algorithm was analyzed and the cyclic iteration structure and the whole parallel pipeline structure was designed respectively from the perspective of hardware implementation.On the basis of the above we further optimized and designed a more flexible partially parallel cuttable structure finally.The structure can cut the hardware circuit structure according to the system performance requirements,which improves the problems of slow data processing in the iterative structure and the large logic resources in the whole parallel pipeline structure.Finally,the behavior description and function simulation of the above structure are completed by hardware description language,and the synthesis and data analysis are carried out on Altera FPGA devices.The results show that the cuttable structure has a smaller logic resource and a lower power consumption on the basis of satisfying the system performance requirements.

关 键 词：SM4算法 分组加密 部分并行 可裁剪 

分 类 号：TN918.4[电子电信—通信与信息系统]