基于FPGA的MMU IP软核设计及实现  

Design and Implementation of MMU IP Softcore based on FPGA

作　　者：刘红伟 梁超广 朱慧惠 潘灵[1] 邵龙[1] 林勤 LIU Hong-wei;LIANG Chao-guang;ZHU Hui-hui;PAN Ling;SHAO Long;LIN Qin(Southwest China Institute of Electronic Technology, Chengdu Sichuan 610036, China;Xi’an Institute of Aviation Industry, Xi’an Shaanxi 710000, China)

机构地区：[1]中国西南电子技术研究所,四川成都610036 [2]航空工业西飞研究院,陕西西安710000

出　　处：《通信技术》2019年第9期2291-2297,共7页Communications Technology

摘　　要：基于Xilinx公司Ultrascale+系列的ZCU102开发板,设计了一个大规模可编程逻辑器件,从armv8处理器外挂的内存颗粒读取大量数据过程时使用的内存管理单元(MemoryManagementUint,MMU)IP软核,并通过ILA调试工具对该IP软核进行了大量数据的读取验证。该MMU实现了将armv8处理器中运行的Linux操作系统产生数据的虚拟地址发送到MMU,在大规模可编程逻辑器件中完成虚拟地址到物理地址的转换,并通过并行AXI总线读取处理器端产生的数据。Based on the ZCU102 development board of Xilinx Ultrascale+ series, a large scale programmable logic device is designed to a large amount of data from the memory granules of armv8 processor. The MMU(memory management unit) IP software core is read and validated by LLA debugging tool. The MMU transmits the virtual address of data generated by Linux operating system running in armv8 processor to MMU, completes the conversion of virtual address to physical address in large-scale programmable logic device, and reads the data generated by processor through parallel AXI bus.

关 键 词：MMU 大规模可编程逻辑器件 虚拟地址 物理地址 

分 类 号：TP273.5[自动化与计算机技术—检测技术与自动化装置]