Thermal resistance matrix representation of thermal effects and thermal design of microwave power HBTs with two-dimensional array layout  

作　　者：Rui Chen Dong-Yue Jin Wan-Rong Zhang Li-Fan Wang Bin Guo Hu Chen Ling-Han Yin Xiao-Xue Jia 陈蕊;金冬月;张万荣;王利凡;郭斌;陈虎;殷凌寒;贾晓雪(Faculty of Information Technology, Beijing University of Technology)

机构地区：[1]Faculty of Information Technology, Beijing University of Technology

出　　处：《Chinese Physics B》2019年第9期373-380,共8页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Grant Nos.61006059 and 61774012);Beijing Municipal Natural Science Foundation,China(Grant No.4143059);Beijing Municipal Education Committee,China(Grant No.KM201710005027);Postdoctoral Science Foundation of Beijing,China(Grant No.2015ZZ-11);China Postdoctoral Science Foundation(Grant No.2015M580951);Scientific Research Foundation Project of Beijing Future Chip Technology Innovation Center,China(Grant No.KYJJ2016008)

摘　　要：Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively.For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance.However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction.Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively.It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance,and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution.By taking a 2 × 6 HBTs array for example, a twodimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power.For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively.For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance.However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction.Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively.It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance,and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution.By taking a 2 × 6 HBTs array for example, a twodimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power.For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.

关 键 词：HETEROJUNCTION BIPOLAR transistors(HBTs) array THERMAL effects THERMAL resistance MATRIX THERMAL design 

分 类 号：O4[理学—物理]