低热梯度导向的三维FPGA互连通道网络架构研究  

Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design

作　　者：高丽江[1,2] 杨海钢 张超[1] GAO Lijiang;YANG Haigang;ZHANG Chao(Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100049

出　　处：《电子与信息学报》2019年第10期2389-2395,共7页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61876172,61704173);北京市科技重大专项课题(Z171100000117019)~~

摘　　要：该文针对3维FPGA(3D FPGA)芯片存在的散热问题,提出具有低热梯度特征的互连网络通道结构,力图解决传统FPGA匀称互连通道设计在芯片堆叠实现上产生的温度非平衡现象。该文建立了3D FPGA的热阻网络模型;对不同类型的通道线对3D FPGA的热分布影响进行了理论分析和热仿真;提出了垂直方向通道网络非均匀分布的3D FPGA通道结构,实验表明,与给定传统FPGA互连通道结构相比,采用所提方法实现的3D FPGA设计架构能够降低76.8%的层间最高温度梯度,10.4%的层内温度梯度。To solve the problem of heat dissipation in Three Dimensional Field Programmable Gate Array Technology(3D FPGA),an interconnect channel architectural design method with low thermal gradient feature is proposed.A thermal resistance network model is established for the 3D FPGA,and theoretical studies and thermal simulation experiments are carried out on the influence of different types of channels on the thermal performance of 3D FPGA.Further,non-uniform vertical direction channel structures of 3D FPGA are proposed.Experiments indicate that 3D FPGA designed using the method proposed can reduce the maximum temperature gradient between different layers by 76.8%and the temperature gradient within the same layer by 10.4%compared with the traditional channel structure of 3D FPGA.

关 键 词：3维现场可编程门阵列 非均匀通道结构 热分布 

分 类 号：TN402[电子电信—微电子学与固体电子学]