适用于现场可编程门阵列I/O通道的可编程延时单元结构设计方法研究  

Research in to the programmable delay element structure design method for field programmable gate array I/O track

作　　者：高丽江[1,2] 杨海钢 韦援丰[1] 李威 GAO Li-jiang;YANG Hai-gang;WEI Yuan-feng;LI Wei(Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China;University of Chinese Academy of Sciences,Beijing 100049,China;Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China)

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100049 [3]中国科学院计算技术研究所,北京100190

出　　处：《微电子学与计算机》2019年第10期1-5,共5页Microelectronics & Computer

基　　金：国家自然科学基金(61876172,61704173)

摘　　要：本文对FPGA芯片输入输出通道模块的可编程延时单元设计方法进行了研究,针对可编程延时单元所需的延时调整范围广、延时调整精度高、延时级数多的特性,提出了一种输入输出信号时序可调整的结构设计方法,以满足总线信号边沿对齐或电路建立与保持时间的要求.所设计的延时链采用粗调延时单元与细调延时单元相结合的方式提高精度和覆盖范围,并在较少的控制向量下,实现了45级延时.延时链延时步进精度为100ps,延时最大值为4.58ns.其功耗和面积分别是传统反相器链结构延时单元的34.5%和55.9%.In this paper,the programmable delay element of the input and output track module of the FPGA chip is studied.By designing the programmable delay element with wide delay adjustment range,high delay adjustment precision and many delay series,the requirements of the delay adjustment of bus signals to align bus edges or meet the requirement of setup/hold time are satisfied.The designmethod is proposed in detail.In the design,the finegrained delay element and coarse-grained delay element are used to increase the step precision and delay range. Finally,the delay element with the precision of 100ps and the range of 4.58ns is implemented under the condition of fewer control vector,lower power dissipation and smaller area.The simulation result indicate that the power and area are only 34.5%and 55.9%compared with the traditional inverter chain structure.

关 键 词：现场可编程门阵列 细调延时单元 粗调延时单元 输入输出通道 

分 类 号：TN402[电子电信—微电子学与固体电子学]