高速NRZ码同步时钟提取设计及FPGA实现  

Synchronous Clock Extraction Design of High Speed NRZ Code and its FPGA Realization

作　　者：徐泽琨 黄明[1] 汪弈舟 李国诚 黄炎[1] XU Ze-kun;HUANG Ming;WANG Yi-zhou;LI Guo-cheng;HUANG Yan(North China University of Technology, Beijing 100041, China)

机构地区：[1]北方工业大学

出　　处：《工业技术创新》2019年第5期28-33,共6页Industrial Technology Innovation

基　　金：北方工业大学信息学院电子系;北京市大学生科学研究与创业行动计划项目资助与支持

摘　　要：为精准提取高速NRZ码元的时钟,设计了过零检测微分型数字锁相环,采用增加/扣除脉冲法进行动态相位调整,用以实现对高速NRZ码元接收序列进行位时钟同步;分析了最大锁定范围和最大锁定频率与本地时钟频率的关系;使用VerilogHDL语言进行代码编写,基于FPGA进行了验证。应用误码仪实测表明:在发送波特率为1Mbps的PN17伪随机序列时,时钟同步后误码率小于10^-7;最高时钟恢复速率可达50Mbps。实际应用中具有很好的适用性和抗干扰性。In order to accurately extract the clock of high-speed NRZ symbols, a zero-crossing detection differential digital phase-locked loop is designed. The dynamic phase adjustment is carried out by adding/ subtracting pulses to achieve bit-clock synchronization of high-speed NRZ symbols receiving sequence. The relationship between the maximum locking range, the maximum locking frequency and the local clock frequency is analyzed. The code is written in Verilog HDL language and verification has been done on the basis of FPGA. The experimental results show that the bit error rate after clock synchronization is less than 10^-7 and the maximum clock recovery rate can reach 50 Mbps when the transmitting baud rate of PN17 pseudo-random sequence is 1 Mbps. It has good applicability and anti-interference in practical applications.

关 键 词：增加/扣除脉冲法 位时钟同步 时钟恢复 FPGA 高速NRZ码 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]