基于JESD204B协议支持大/小端模式的加扰器  

A Scrambler Supporting Big/Little Endian Based on JESD204B Protocol

作　　者：姚佳 蒲杰[2] 何基 吴燕青 YAO Jia;PU Jie;HE Ji;WU Yanqing(College of Optoelec.Engineer.,Chongqing University of Posts and Telecommunications,Chongqing400065,P.R.China;Science and Technology on Analog Integrated Circuit Laboratory,Chongqing400060,P.R.China)

机构地区：[1]重庆邮电大学光电工程学院,重庆400065 [2]模拟集成电路国家重点实验室,重庆400060

出　　处：《微电子学》2019年第5期637-642,共6页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(6142802WD201805)

摘　　要：设计了一种基于JESD204B协议、支持大/小端模式且具有旁路能力的四字节并行加扰器。在并行加扰/解扰原理的基础上,采用四字节并行处理技术,加快了扰码的产生效率。该加扰器支持大/小端模式,根据不同需求可自行选择不同模式。采用Verilog HDL语言对电路进行设计,利用Modelsim进行功能仿真,在Quartus II软件上进行实现。该加扰器可直接移植到基于JESD204B协议的收发器。A quat-byte parallel scrambler with bypass ability and supported big/little endian was designed based on JESD204Bprotocol.On the basis of further study of parallel scrambling/descrambling principle,the generation efficiency of scrambling was accelerated by using quat-byte parallel processing technology.At the same time,the scrambler supported big/little endian,and different modes could be selected according to different requirements.The scrambler was designed by Verilog HDL language.The functional simulation was completed by Modelsim,and the circuit was implemented by Quartus II software.It could be transplanted directly into the transceiver circuit based on JESD204Bprotocol.

关 键 词：JESD204B协议 大/小端模式 加扰器 

分 类 号：TN919.3[电子电信—通信与信息系统]