基于FPGA的双二进制Turbo译码器的硬件实现  

Hardware Implementation of a Duo-Binary Turbo Decoder Based on FPGA

作　　者：林毅 董妮娅 LIN Yi;DONG Niya(National Defense Inform.Engineer.Technol.Resear.Instit.,Chongqing Univ.of Posts and Telecommun.,Chongqing400065,P.R.China;College of Mobile Telecommun.,Chongqing Univ.of Posts and Telecommun.,Chongqing400065,P.R.China)

机构地区：[1]重庆邮电大学国防信息工程技术研究院,重庆400065 [2]重庆邮电大学移通学院,重庆400065

出　　处：《微电子学》2019年第5期664-669,共6页Microelectronics

基　　金：国家科技重大专项基金资助项目(2018ZX03001026-002);重庆市教委科技研究项目(KJ1600436)

摘　　要：针对宽带电力载波通信中采用的双二进制Turbo译码器,给出了一种基于FPGA的并行实现方案。该方案采用无交叠滑动窗的多路并行分块以及流水线结构,以Xilinx的XC7K410T为硬件平台,采用Verilog硬件描述语言来设计实现,给出了不同并行块数的实现结果。当数据块长为520字节时,4次迭代后,数据速率可达200Mbit/s。测试结果表明,该方案占用资源少、译码速度快、性能指标满足要求,具有较好的应用价值。A parallel implementation scheme based on FPGA was presented for the duo-binary turbo decoder which was used in broadband power carrier communications.A multi-channel parallel block and pipeline structure without overlapping sliding windows was adopted.The Xilinx XC7K410Twas used as the hardware platform,and was designed and implemented by Verilog-HDL.The implementation results of different parallel block numbers were given.When the data block length was 520bytes,the data rate could reach 200Mbit/s after 4iterations.The test result showed that this scheme had less resource occupation and faster decoding speed,and had met the performance requirements.It had better practicability and application values.

关 键 词：双二进制Turbo码 并行译码 FPGA 滑动窗 

分 类 号：TN911.22[电子电信—通信与信息系统]