一种新型跨时钟域边沿检测同步器  

A Novel Edge Synchronizer for Clock Domain Crossing

作　　者：戴晶星 李富华[1] 刘学观[1] 黄君山 侯汇宇 DAI Jingxing;LI Fuhua;LIU Xueguan;HUANG Junshan;HOU Huiyu(School of Electronic and Information Engineering,Soochow University,Suzhou,Jiangsu 215006,P.R.China;Suzhou Gemeixin Microelectronic Co.,Ltd.,Suzhou,Jiangsu 215000,P.R.China)

机构地区：[1]苏州大学电子信息学院,江苏苏州215006 [2]苏州格美芯微电子有限公司,江苏苏州215000

出　　处：《微电子学》2019年第5期703-707,723,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61671315)

摘　　要：传统的边沿检测同步器由触发器构成,被同步的数据至少需要在新时钟域的1个时钟周期内保持有效。提出一种新型边沿检测同步器,由两相无重叠时钟产生电路、5个锁存器等构成。理论分析结果表明,新型边沿检测同步器中数据稳定时间的极限值为新时钟域的0.75个周期。基于Nuvoton 0.35μm 2P3MCMOS工艺,采用Verilog_XL工具进行仿真验证。结果表明,新型边沿检测同步器的时序与理论分析一致。采用0.8个新时钟域周期的实例,验证了新型边沿检测同步器的工作正常,同步器的分辨率有所提高。The traditional edge synchronizer is composed of flip-flops,whose synchronized data needs to maintain stable for at least 1cycle of the new clock domain.A novel edge synchronizer was proposed which consisted of 5 latches,circuits for generating a two-phase non-overlapping clock and so on.The logical analysis of the synchronizer was carried out through theoretical analysis.The synchronizer was simulated by Verilog_XL based on Nuvoton 0.35 μm 2P3MCMOS process.Theoretical analysis showed that the limit of data stabilization time was 0.75cycles of the new clock domain in the novel synchronizer.Besides,simulation results showed that the timing of the novel edge synchronizer was consistent with that of theoretical analysis.An example of 0.8cycles of new clock domain was used for verification.It was verified that the synchronizer worked normally and had improved the synchronizer resolution time.

关 键 词：跨时钟域 边沿检测同步器 非重叠时钟 

分 类 号：TN432[电子电信—微电子学与固体电子学]