基于BFS和FPGA-CPU的混合加速器设计  

Design of Hybrid Accelerator Based on BFS and FPGA-CPU

作　　者：郭小波[1,2] 杨光露 GUO Xiao-bo;YANG Guang-lu(School of Computer Science and Engineering,Henan Institute of Engineering,Zhengzhou 451191,China;Key Laboratory of Grain Information Processing and Control Ministry of Education,Zhengzhou 450002,China;Nanyang Cigarette Factory,China Tobacco Henan Industrial Co.,Ltd.,Nanyang 473007,China)

机构地区：[1]河南工程学院计算机学院,郑州451191 [2]粮食信息处理与控制教育部重点实验室,郑州450002 [3]河南中烟工业有限责任公司南阳卷烟厂,河南南阳473007

出　　处：《火力与指挥控制》2019年第10期95-100,共6页Fire Control & Command Control

基　　金：河南省科技厅科技攻关计划项目(182102310025);粮食信息处理与控制教育部重点实验室项目(KFJJ-2016-201);河南工程学院博士基金资助项目(Dkj2018002)

摘　　要：为了实现由软件和硬件执行小世界图搜索的加速器系统,提出了一种在单芯片FPGA-CPU异构硬件平台上基于广度优先搜索算法实现的混合加速器系统设计;提出了采用线性代数语言实现的BFS;提出了一种处理单元结构,它由一个负责与主存储器全部交互的后端、用于执行布尔塥运算的前端和一个距离生成器构成;在Zed-Board平台上设计了一种采用Xilinx Zynq Z7020 FPGA-CPU 混合结构的实际加速器系统。实验结果表明,设计的混合加速器不仅能够实现小世界图的快速搜索,而且相比于目前其他先进的基于BFS算法的混合加速器结构有更好的加速性能。In order to achieve an accelerator system for implementation of small world graph search by software and hardware,a hybrid accelerator system based on breadth first search algorithm is proposed on a heterogeneous hardware platform, which consists of a single chip FPGA-CPU. Firstly, it adopts a BFS which is implemented by linear algebra language. Secondly, it presents a processing unit architecture which is composed of a backend responsible for all interaction with main memory, a frontend for performing the operator and a distance generator. Finally,a practical accelerator system with Xilinx Zynq Z7020 and FPGA-CPU hybrid structure is designed on the ZedBoard platform. The experimental results show that the proposed hybrid accelerator can not only implement the rapid search of small world graph, but also has better acceleration performance compared with the other advanced hybrid accelerator structure based on BFS algorithm.

关 键 词：广度优先搜索 小世界图 布尔运算 存储结构 处理单元 带宽利用率 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]