动态分层及其在CMOL电路缺陷容忍映射优化中的应用  

Dynamic Stratifying and Its Applications in Defect-Tolerant Mapping Optimization for CMOL Circuits

作　　者：查晓婧 夏银水[1] 储著飞[1] Zha Xiaojing;Xia Yinshui;Chu Zhufei(School of Information Science and Engineering,Ningbo University,Ningbo 315211)

机构地区：[1]宁波大学信息科学与工程学院

出　　处：《计算机辅助设计与图形学学报》2019年第8期1457-1466,共10页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(61571248,61501268)

摘　　要：由于CMOS/纳米混合电路(CMOL)中存在高缺陷率,缺陷容忍映射成为解决CMOL电路实用化的必需方法.针对传统的整体缺陷容忍方法中存在的耗时、难以求解大电路等问题,提出基于动态分层的缺陷容忍映射优化方法.首先对电路的缺陷进行了分类,然后以缺陷数递减的方式对CMOL电路进行动态分层,最后采用修改的禁忌算法在分层后的CMOL电路中验证所提出方法的性能.ISCAS测试电路的实验结果表明,与已有方法相比,文中方法在线长和映射速度方面有较明显优势.Due to high defect rate in CMOS/nanowire/molecular hybrid (CMOL) circuits, defect-tolerant mapping is essential to solve the practical application of CMOL circuits. For the time-consuming and difficulty to map large circuits in traditional whole defect-tolerant methods, a defect-tolerant mapping optimization method based on dynamically stratifying CMOL circuit is proposed. Firstly, circuit defect types are classified. Then, the CMOL circuit is dynamically stratified by the decreasing number of the defects. Finally, modified Tabu search algorithm is employed to verify the performance of the proposed method in the stratified CMOL circuit. The experiment results of the ISCAS benchmarks show that compared with existing methods, the proposed method has advantages in terms of wirelength and CPU time.

关 键 词：CMOL电路 缺陷容忍 动态分层 禁忌搜索算法 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]