基于DDS+PLL的低相噪频率合成器设计  

Design of Low Phase Noise Frequency Synthesizer Based on DDS+PLL

作　　者：宋雪莹 崔永俊[1] 张祥 刘坤 SONG Xueying;CUI Yongjun;ZHANG Xiang;LIU Kun(Key Laboratory of Instrumentation Science and Dynamic Measurement,Ministry of Education,Key Laboratory of National Defense Science and Technology on Electronic Measurement,School of Instrument and Electronics,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室电子测试技术国防科技重点实验室仪器与电子学院

出　　处：《电子器件》2019年第4期947-952,共6页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(61335008)

摘　　要：为了解决传统信号源输出信号种类单一、频率固定、实时调节能力差、噪声大等问题,设计了基于DDS和PLL的频率合成器。该频率合成器以FPGA为控制单元,选用DDS芯片AD9910,以及低噪声数字鉴相芯片ADF4108,用DDS直接激励PLL,能够稳定输出高达2.85 GHz的信号。该频率合成器具有多种波形输出,频率、相位可变,可实时调频调相等功能。经测试,相位噪声优于-116 dBc/Hz@1 MHz,满足实际应用需求。In order to solve the problems of traditional signal source such as single output signal type,fixed frequency,poor real-time adjustment capability large noise,a frequency synthesizer based on DDS and PLL is designed.The frequency synthesizer uses FPGA as control unit,selects DDS chip AD9910 and low noise digital phase detector chip ADF4108,uses DDS to directly excite PLL,and can stably output signals as high as 2.85 GHz.The frequency synthesizer has various waveform outputs,variable frequency and phase,and real-time frequency modulation and modulation functions.After testing,the phase noise is better than-116 dBc/Hz@1 MHz,which meets the practical application requirements.

关 键 词：DDS PLL 频率合成器 FPGA AD9910 ADF4108 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]