基于UVM的FPGA通用接口测试平台设计  

Design of Universal Interface Test Platform for FPGA Based on UVM

作　　者：王涛[1] 黄坤超[1] 李晨阳[1] WANG Tao;HUANG Kunchao;LI Chenyang(The Tenth Institute of China Electronic Technology Group,Chengdu 610036,China)

机构地区：[1]中国电子科技集团公司第十研究所

出　　处：《测试技术学报》2019年第5期443-449,共7页Journal of Test and Measurement Technology

摘　　要：采用层次化设计、通用数据库共享、事件同步化处理、脚本执行等方法,研究了在UVM验证平台中引入高层次化序列分类设计,利用一种通用数据库共享方式替换专用端口进行组件间的信息传递,通过事件触发方式解决组件间的同步化,克服了平台难以适应多重验证环境的局限性,实现了测试指令与测试设计分离,测试设计与被测设计分离,测试平台的可重用性得到进一步提升.平台提供可视化的人机交换界面和脚本命令两种执行方式,通过项目测试结果分析和对比,新的平台克服了UVM验证平台的复杂性,具有简洁、透明的处理方式,能够同时满足多种接口测试需要,是一种建立FPGA通用接口自动化测试平台的有效方法.By using the methods of hierarchical design,common database sharing,event synchronization processing and script execution,this paper studies the introduction of high-level sequence classification design in UVM verification platform.A common database sharing method is used to replace the special ports for information transfer between components and The synchronization between components is solved by event triggering method,which overcomes the limitation of the platform that is difficult to adapt to multiple verification environments,and realizes the separation of test instructions and test design and the separation of test design and tested design,so that the reusability of test platform is further enhanced.The platform provides two execution modes of visual human-machine exchange interface and script command.Through analysis and comparison of project test results,the new platform overcomes the complexity of the UVM verification platform.has a concise and transparent processing mode,and can meet the needs of multiple interface testing at the same time.Using the new platform is an effective method for establishing FPGA universal interface automatic test platform.

关 键 词：FPGA UVM 测试平台 数据库 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]