一种高效多标准视频解码器架构研究与设计  

Research and Design of an Efficient Multi-standard Video Decoder Architecture

作　　者：刘慧超 王志君[1] 梁利平[1] LIU Huichao;WANG Zhijun;LIANG Liping(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《湖南大学学报（自然科学版）》2019年第10期117-124,共8页Journal of Hunan University:Natural Sciences

基　　金：中国科学院知识创新项目(KGCX2-YW-134)~~

摘　　要：针对目前视频解码器实现方案存在的灵活度低、开发周期长、不能适应快速变化的算法升级等问题,提出一种面向多种视频编解码标准的通用视频解码器架构设计方案.采用软硬件协同设计方法,基于可编程同构多核处理器+协处理器的硬件架构,同构多核处理器采用指令级和任务级并行加速,协处理器采用硬件定制单元实现矢量加速,同时利用分布式片上便笺式存储器(Scratchpad Memory,SPM)代替数据Cache实现高效的数据存储系统,以应用广泛的H.264视频标准为验证实例.实验结果表明,基于本文所提架构实现的H.264视频解码器高效可行,平均并行加速比为9.12,相比于传统多核并行解码算法提高了1.31倍.Aiming at the problems such as low flexibility,long development cycle,and incapability of adapting to rapidly changing algorithms for current video decoder implementation solutions,a generic video decoder architecture design scheme for multiple video coding and decoding standards is proposed using software and hardware collaboration.The methodology of the design is based on a programmable homogeneous multi-core processor and coprocessor hardware architecture.The homogeneous multi-core processor uses instruction-level and task-level parallel acceleration.The coprocessor uses a hardware customization unit to achieve the vector acceleration,while it uses distributed on-chip scratchpad memory instead of data cache to achieve an efficient data storage system.Taking the H.264 video standard widely used as an example,the experimental results show that the H.264 video decoder based on the architecture proposed in this paper is highly efficient and feasible,with an average speed-up of 9.12,which is 1.31 times better than the traditional multi-core parallel decoding algorithm.

关 键 词：多标准 视频解码器 可编程 协处理器 便笺存储器 H.264解码器 架构设计 

分 类 号：TN919.3[电子电信—通信与信息系统]