一种新型的12位SAR ADC设计  

Design of a novel 12-bit SAR ADC

作　　者：孙帆 黄海波[1] 卢军[1] 陈宇峰[1] Sun Fan;Huang Haibo;Lu Jun;Chen Yufeng(School of Electrical&Information Engineering,Hubei University of Automotive Technology,Shiyan 442002 China)

机构地区：[1]湖北汽车工业学院电气与信息工程学院

出　　处：《电子技术应用》2019年第11期36-41,共6页Application of Electronic Technique

基　　金：湖北省中央引导地方科技发展专项(2018ZYYD007)

摘　　要：设计了一种12位精度,200 kS/s采样率的逐次逼近型模数转换器(SAR ADC)。针对传统的电容开关切换算法的大电容面积和高功耗,采用一种新型的电容开关切换算法,提高了转换精度,降低了功耗。此外,比较器电路采用一种全差分动态比较器和静态预放大比较器分时工作的方法,进一步降低了功耗。基于TSMC 0.18μm CMOS工艺,对电路进行了设计和仿真。仿真结果表明,在采样率为200 kS/s时,信号噪声失真比(SNDR)为70.94 dB,有效位数(ENOB)为11.49位,功耗为22μW,优值系数(FOM)为38.2 fJ/(Conversion·step)。A 12-bit 200 kS/s sampling rate successive approximation analog-to-digital converter(SAR ADC)is designed in this paper.Aiming at the large capacitance area and high power consumption of traditional capacitor switching algorithm,a new capacitor switching algorithm is adopted which greatly improves conversion accuracy and reduces power consumption.In addition,the comparator circuit of a fully differential dynamic comparator and a static preamplifier comparator working in a time-sharing manner is utilized to reduce the power consumption further.The circuit is designed and simulated in TSMC 0.18μm CMOS process.The simulation results show that,at a sampling rate of 200 kS/s,the signal-to-noise ratio(SNDR)is 70.94 dB,the effective number of bit(ENOB)is 11.49 bit,the power consumption is 22μW,and the figure-of-merit(FOM)is 38.2 fJ/(Conversion·step).

关 键 词：逐次逼近模数转换器 新型电容开关切换算法 分时工作比较器 有效位数 

分 类 号：TN432[电子电信—微电子学与固体电子学]