基于状态机控制的硬件Page Walk方案与实现  

A FSM-Based Page Walker Design and Implementation

作　　者：路冬冬 王炳凯 杜鑫 LU Dongdong;WANG Bingkai;DU Xin(Shanghai High Performance IC Design Center,Shanghai 201204;School of Electronic and Engineering,University of Electronic Science and Technology of China,Chengdu 610054)

机构地区：[1]上海高性能集成电路设计中心,上海201204 [2]电子科技大学电子科学与工程学院,成都610054

出　　处：《计算机与数字工程》2019年第11期2733-2737,共5页Computer & Digital Engineering

基　　金：核高基“国产处理器核心性能提升研究”(编号:2018ZX01029101)资助

摘　　要：在现代微处理器中,虚实地址代换一般处于Cache访问的关键路径上,旁路转换缓冲(TLB)作为虚实地址代换的专用缓冲,用于提高虚实地址代换的速度。当不命中TLB时,需要逐级查找页表以获取代换后的物理地址。论文提出一种基于状态机控制的硬件自动查找页表并装填TLB的方案,并给出具体实现;同时,结合页表结构Cache,对状态机进行优化,进一步提升硬件查找页表的速度,降低TLB Miss的处理开销。In modern processors,virtual address to physical address translation is usually in the critical path of cache access.To leverage the memory access locality,processors use TLB,a special kind of cache,to cache the recent translation information and provide a fast translation.TLB miss requires page walks to translate the virtual address.This paper proposes a FSM-based page walker,and gives the specific implementation.The FSM is optimized with page structure cache to further improve the performance of page walks.

关 键 词：虚实地址代换 旁路转换缓冲 页表 页表查找 页表结构Cache 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]