基于全碳化硅功率组件的叠层母排优化设计研究  

Optimum Design of Planer Busbar Based on All-silicon Carbide Power Module

作　　者：朱俊杰[1] 原景鑫 聂子玲[1] 徐文凯 韩一 ZHU Junjie;YUAN Jingxin;NIE Ziling;XU Wenkai;HAN Yi(National Key Laboratory for Vessel Intergrated Power System Technology(Naval University of Engineering),Wuhan 430033,Hubei Province,China)

机构地区：[1]舰船综合电力技术国防科技重点实验室(海军工程大学)

出　　处：《中国电机工程学报》2019年第21期6383-6393,共11页Proceedings of the CSEE

基　　金：国家重点基础研究发展计划(973计划)(2015CB251004);国家自然科学基金重大项目(51490681);国防科技重点实验室基金项目(614221704080517)~~

摘　　要：为减小全Si C功率组件开关振荡,满足高功率密度对功率器件的应用要求。定量分析三相两电平拓扑叠层母排元器件布局关系,建立考虑自感和互感的叠层母排数学模型,基于数学模型计算单个电容和2个电容对应的母排回路杂散电感等效值,仿真分析3个电容以上对应的叠层母排回路杂散电感等效值。计算与仿真结果均表明,随着支撑电容数量的增加,回路杂散电感逐渐减小,并且一致性更好。通过分析各支路杂散电感,优化了直流母线端口布局;通过双脉冲实验验证了叠层母排优化后抑制开关振荡的效果。实验结果表明,虽然优化后的功率组件开关时间及开关损耗有所增加,但开关振荡得到有效抑制,能更好地满足高功率密度应用场合对安全性能的需求。In order to reduce switching oscillation of allSi C power modules and meet the application requirements of high power density for power devices. The layouts of three-phase two-level topological planer busbar elements were analyzed quantitatively, and a mathematical model of planer busbar elements considering self-inductance and mutual inductance was established. Based on the mathematical model, the equivalent values of stray inductance of the planer busbar circuit corresponding to a single capacitor and two capacitors were calculated. The equivalent stray inductance of the planer busbar circuit corresponding to the capacitance above was calculated and simulated. The results show that with the increase of the number of supporting capacitors, the stray inductance of the circuit decreases gradually, and the consistency is better. By analyzing the stray inductance of each branch, the layout of DC bus port was optimized, and the effect of restraining switching oscillation was verified by double pulse experiment. The experimental results show that although the switching time and switching loss of the optimized power module increase, the switching oscillation can be effectively suppressed, which can better meet the security requirements of high power density applications.

关 键 词：叠层母排数学模型 全SiC功率组件 杂散电感 开关振荡 

分 类 号：TN323[电子电信—物理电子学]