一种基于FPGA的高精度定时内插间隔估计方法  

Estimated Method of High-Precision Timing Interpolation Interval based on FPGA

作　　者：陈章 安君帅 CHEN Zhang;AN Jun-shuai(Nanjing Panda Handa Technology Co.,Ltd.,Nanjing Jiangsu 210001,China)

机构地区：[1]南京熊猫汉达科技有限公司

出　　处：《通信技术》2019年第12期3080-3084,共5页Communications Technology

摘　　要：针对全数字接收机中位定时同步环定时恢复精度低、实现难度大等问题,提出了一种基于FPGA的高精度定时恢复内插间隔估计方法。该方法以系统主时钟作为基准进行内插间隔估计和定时补偿,可获得低于系统主时钟的估计精度和恢复精度,且工程实现复杂度低、占用资源小、结构灵活性强,对于内插滤波器及内插定时误差估计算法不做特殊要求,具有较强的工程实现通用性。仿真结果表明,该方法具有更高的定时恢复精度。Aiming at the problems of low-precision and large implementation difficulty of the symbol timing synchronization loop in the all-digital receivers,an FPGA-based high-precision timing recovery interpolation interval estimation method is proposed.This method uses the system master clock as a reference to perform interpolation interval estimation and timing compensation,and can obtain lower estimation accuracy and recovery accuracy than the system master clock.Meanwhile,The method has low implementation complexity,small resource occupation and strong structural flexibility,which does not require special requirements for interpolation filters and interpolation timing error estimation algorithms and has strong engineering implementation versatility.Simulation results indicate that this method has higher timing recovery accuracy.

关 键 词：全数字接收机 位定时同步 内插间隔估计 FPGA 

分 类 号：G316[文化科学]