应用于K波段分数分频频率综合器的多模分频器设计与优化  

Design and Optimization of Multi-Modulus-Divider for K-Band Fractional-N Frequency Synthesizer

作　　者：王征晨 武照博 齐全文 王兴华[1] WANG Zheng-chen;WU Zhao-bo;QI Quan-wen;WANG Xing-hua(Beijing Silicon SoC Engineering Research Center,School of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China)

机构地区：[1]北京理工大学信息与电子学院北京市硅基高速片上系统工程技术研究中心

出　　处：《北京理工大学学报》2019年第11期1187-1191,共5页Transactions of Beijing Institute of Technology

基　　金：国家自然科学基金资助项目(61301006)

摘　　要：基于TSMC 90 nm CMOS工艺设计一款多模分频器,可以实现的分频比的范围为32~39.详细介绍了多模分频器的各部分模块,包括双模预定标器、S计数器和P计数器,分析并且讨论了P计数器加入与不加入重新定时电路的时序图.本文设计的分频器应用于K波段高速分数分频频率综合器.测试结果表明应用改进后的多模分频器,频率综合器的带内噪声可以优化15 dB,频偏10 kHz和频偏1 kHz的相位噪声可达到81.30 dBc/Hz和72.44 dBc/Hz.A multi-modulus-divider(MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve-81.3 dBc/Hz and-72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.

关 键 词：多模分频器 分数分频频率综合器 重新定时电路技术 

分 类 号：TN432[电子电信—微电子学与固体电子学]