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作 者:阮伟华 王海鹏 RUAN Weihua;WANG Haipeng(Electronic Information Engineering College,Sanjiang University,Nanjing 210012,China)
机构地区:[1]三江学院电子信息工程学院
出 处:《集成技术》2019年第6期1-10,共10页Journal of Integration Technology
基 金:国家自然科学基金项目(61801262);江苏省高等学校自然科学研究项目(18KJB10039);三江学院科研资助项目(2018SJKY012)
摘 要:该文介绍了4种变速箱设计方法,并对它们进行时序分析。通过对比单元数量(面积)、功耗、速度及稳定性,选择了一种基于轮循存储方式的变速箱应用到100GE物理编码子层电路中。该变速箱可以在一段时间范围内开始输出,克服了输入输出时钟相位差的影响,提高了电路的速度和稳定性。经过结构优化及流水线结构设计,该变速箱的时钟速度超过700 MHz。另外,采用0.18μm互补金属氧化物半导体工艺对物理编码子层电路进行流片,测试结果表明该电路能够以100 Gb/s速率稳定工作,进一步证明了变速箱设计的正确性。In this paper, four design methods of gearbox are introduced, and their timing analysis is carried out. By comparing the number of cells(area), power consumption, speed and stability, a gearbox based on roundrobin saving mode is selected and applied to 100 GE physical coding sublayer circuit. It can take out the output value within a certain range, which overcomes the influence of phase difference between input and output clocks and greatly improves the speed and stability of the circuit. After structure optimization and pipeline design, the gearbox can work stability at the clock frequency of over 700 MHz and meet the design requirement. The physical coding sublayer circuit which including the gearbox has been taped out in 0.18 μm complementary metal oxide semiconductor technology and measured results show that it can work properly at speed of 100 Gb/s.
分 类 号:TN47[电子电信—微电子学与固体电子学]
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