基于高分辨率TDC的快速全数字锁相环  

Fast all digital phase-locked loop based on high resolution TDC

作　　者：揭灿 邹家轩[1] 王栋[1] 谢雨蒙 钟梁 吴建东 JIE Can;ZOU Jiaxuan;WANG Dong;XIE Yumeng;ZHONG Liang;WU Jiandong(The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214000,China;School of Mechanical and Electronic Information,China University Geosciences(Wuhan),Wuhan 430074,China)

机构地区：[1]中国电子科技集团第五十八研究所,江苏无锡214000 [2]中国地质大学(武汉)机械与电子信息学院,湖北武汉430074

出　　处：《电视技术》2019年第8期65-69,共5页Video Engineering

基　　金：国家自然科学基金(61601334)

摘　　要：针对时间数字转换器(Time-to-Digital Converter,TDC)的精度低,全数字锁相环(All Digital Phase-Locked Loop,ADPLL)的锁定时间长问题,设计了一种新型全数字锁相环。本设计中的TDC优化了差分延迟线法结构,提高了量化相位差信号的分辨率;在数控振荡器(Digital Controlled Oscillator,DCO)中内嵌的相调电路能快速调整反馈信号的相位,缩短环路的锁定时间。最后在Xilinx VC709评估套件上进行电路设计与仿真验证。结果表明,该ADPLL的量化误差不大于0.25 ns,在三个参考信号时钟周期内即可完成锁定。该全数字锁相环具有锁定时间短、捕获精度高等优势。Aiming at the problems that time-to-digital converter(TDC)suffers a low precision and all digital phase-locked loop(ADPLL)locks signal for a longer time,this paper proposes a new ADPLL.The new TDC optimizes the structure of differential delay line method and improves the resolution of the quantized phase difference signal.The phase-adjusting circuit embedded in the digital controlled oscillator(DCO)can quickly adjust the phase of the feedback signal and short the lock time of loop.Finally,circuit design and simulation verification are carried out on Xilinx VC709 evaluation kit.The verification results show that the quantization error of the ADPLL is restricted within 0.25 ns,and the loop can be locked in three reference signal clock cycles.The new design of ADPLL has the advantages of short locking time and high capture accuracy.

关 键 词：全数字锁相环 时间数字转换器 数控振荡器 差分延迟线法 抽头延迟线法 

分 类 号：TN911.8[电子电信—通信与信息系统]