一种基于预判机制的极化码译码算法及VLSI架构  

A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture

作　　者：杜高明[1] 胡国庆 林青 张多利[1] 宋宇鲲[1] 欧阳一鸣 DU Gao-ming;HU Guo-qing;LIN Qing;ZHANG Duo-li;SONG Yu-kun;Ouyang Yi-ming(School of Electronic Science Applied Physics,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]合肥工业大学电子科学与应用物理学院

出　　处：《微电子学与计算机》2019年第12期11-15,20,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61474036);教育部IC设计网上合作研究中心(JSGG20170413153845042)

摘　　要：本文提出一种基于对数似然比的预判机制,根据每层对数似然比符号直接判决分裂成"1"或者"0"和固定比特层直接分裂成已知比特,旨在减少路径分裂以及通过直接继承上一层路径度量值的方式,移除冗余的路径度量值计算.基于该机制,我们设计码长N=1 024,码率R=0.5,列表宽度L=2的VLSI硬件架构.实验结果表明,其工作频率在384 MHz下,能达到约160 Mbps的吞吐率,延迟降低约51%.This paper proposes a pre-judgment mechanism based on log-likelihood ratio, reducing redundant split for SCL(RRS-SCL). According to the log-likelihood ratio symbol decision of each layer, it is split into "1" or "0" and the fixed bit layer are directly split into known bits, which aims to reduce path splitting and remove redundant path metric calculations by directly inheriting the path metrics from the previous layer. Based on the scheme, we design RRS-SCL VLSI architecture with code length N=1024, the code rate R=0.5, and the list width L=2. The experimental results show that the throughput can be achieved at 160 Mbps under 384 MHz and delay is reduced by approximately 51%.

关 键 词：极化码 串行抵消列表 预判机制 减少路径分裂 冗余计算 

分 类 号：TN47[电子电信—微电子学与固体电子学]