Contact etch process optimization for RF process wafer edge yield improvement  

作　　者：Zhangli Liu Bingkui He Fei Meng Qiang Bao Yuhong Sun Shaojun Sun Guangwei Zhou Xiuliang Cao Haiwei Xin 

机构地区：[1]Shanghai Huahong Grace Semiconductor Manufacturing Corporation

出　　处：《Journal of Semiconductors》2019年第12期97-100,共4页半导体学报（英文版）

基　　金：supported by Shanghai Rising-Star Program (B type) (No. 18QB1401900)

摘　　要：Radio-frequency(RF)process products suffer from a wafer edge low yield issue,which is induced by contact opening.A failure mechanism has been proposed that is based on the characteristics of a wafer edge film stack.The large step height at the wafer's edge leads to worse planarization for the sparse poly-pattern region during the inter-layer dielectric(ILD)chemical mechanical polishing(CMP)process.A thicker bottom anti-reflect coating(BARC)layer was introduced for a sparse poly-pattern at the wafer edge region.The contact open issue was solved by increasing the break through(BT)time to get a large enough window.Well profile and resistance uniformity were obtained by contact etch recipe optimization.Radio-frequency(RF) process products suffer from a wafer edge low yield issue, which is induced by contact opening. A failure mechanism has been proposed that is based on the characteristics of a wafer edge film stack. The large step height at the wafer’s edge leads to worse planarization for the sparse poly-pattern region during the inter-layer dielectric(ILD)chemical mechanical polishing(CMP) process. A thicker bottom anti-reflect coating(BARC) layer was introduced for a sparse poly-pattern at the wafer edge region. The contact open issue was solved by increasing the break through(BT) time to get a large enough window. Well profile and resistance uniformity were obtained by contact etch recipe optimization.

关 键 词：bottom anti-reflect coating break through wafer edge PLANARIZATION 

分 类 号：TN3[电子电信—物理电子学]