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作 者:Pengcheng Liu Xiaojun Wang S.R.Chaudhry Khalid Javeed Yue Ma Martin Collier
机构地区:[1]School of Electrical and Computer Engineering,Dublin City University,Dublin,Ireland. [2]Department of Computer Engineering,Bahria University,Islamabad,Pakistan [3]School of Computer Science,Beijing University of Posts and Telecommunications,Beijing,100876,China
出 处:《Computers, Materials & Continua》2018年第12期353-363,共11页计算机、材料和连续体(英文)
基 金:This work was supported by the National Natural Science Foundation of China under grant number 61471055;European Horizon 2020 INPUT project“In-Network Programmability for next-generation personal Cloud service support”,www.input-project.eu,under grant agreement number 644672.
摘 要:The combination of traditional processors and Field Programmable Gate Arrays(FPGA)is shaping the future networking platform for intensive computation in resource-constrained networks and devices.These networks present two key challenges of security and resource limitations.Lightweight ciphers are suitable to provide data security in such constrained environments.Implementing the lightweight PRESENT encryption algorithm in a reconfigurable platform(FPGAs)can offer secure communication service and flexibility.This paper presents hardware acceleration of security primitives in SDN using NETFPGA-10G.We implement an efficient design of the PRESENT algorithm for faster,smaller and lower power consumption hardware circuit using Verilog.We evaluate the performance of the hardware and software implementations of PRESENT.Experimental results prove that the proposed hardware design is a viable option for use in resource constrained devices in future networks and their applications.
关 键 词:Lightweight cipher NETFPGA openFlow RESENT encryption
分 类 号:TP3[自动化与计算机技术—计算机科学与技术]
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