基于Verilog语言的UART串口协议实现新方法  

A new method to implement UART serial port protocol based on Verilog language

作　　者：朱鑫 付海昊 刘东明[1] ZHU Xin;FU Hai-hao;LIU Dong-ming(Northeast petroleum university)

机构地区：[1]东北石油大学

出　　处：《科技成果纵横》2019年第20期28-30,共3页

摘　　要：提出了一种采用Verilog语言中位拼接语法实现UART串口通信协议的新方法,并通过Altera FPGA对程序进行验证。该方法程序简洁,仅通过一条语句实现了UART发送协议的核心功能,且包含奇偶校验位,其中数据位和停止位位宽任意可调。避免了其他方法中复杂的状态判断过程,降低了程序复杂度,提供了一种简洁清晰的编程思路。UART接收协议同样采用这一思路实现。A new method of realizing UART serial port communication protocol using Verilog language median splicing grammar is proposed,and the program is verified by Altera FPGA.This method program is simple,only through a statement to achieve the core function of UART transmission protocol,and contains parity bits,where the data bit and stop bit width are adjustable.It avoids the complicated state judgment process in other methods,reduces the program complexity,and provides a concise and clear programming idea.The UART receiving protocol also adopts this idea.

关 键 词：VERILOG语言 位拼接 UART串口 FPGA 

分 类 号：N01[自然科学总论—科学技术哲学]