用于SAR ADC的低开销电容开关时序设计  

A Low Overhead Capacitor Switching Scheme Applied in SAR ADC

作　　者：张存德 宋鑫宇 虞致国 魏敬和[2] 顾晓峰 ZHANG Cunde;SONG Xinyu;YU Zhiguo;WEI Jinghe;GU Xiaofeng(Engineer.Res.Center of Internet of Things Technol.Appl.of Ministry of Education,Dep.of Elec.Engineer.,Jiangnan Univ.,Wuxi,Jiangsu 214122,P.R.China;The 58th Res.Inst.of CETC,Wuxi,Jiangsu 214035,P.R.China)

机构地区：[1]江南大学电子工程系物联网技术应用教育部工程研究中心,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2019年第6期750-754,共5页Microelectronics

基　　金：江苏省研究生科研与实践创新计划项目(SJCX17_0510,SJCX18_0647);中央高校基本科研业务费专项资金资助项目(JUSRP51510)

摘　　要：逐次逼近型模数转换器(SAR ADC)中,数模转换器单元(DAC)是能耗和面积的主要来源之一。为了降低DAC的能耗和面积,提出了一种低开销电容开关时序,以此设计了DAC的结构,并进行逻辑实现。相比于传统型开关时序,该电容开关时序使得DAC的能耗降低了98.45%,面积减小了87.5%。基于该电容开关时序实现了一种12位SAR ADC。仿真结果表明,在1.2 V电源电压、100 kS/s采样速率的条件下,该ADC功耗为12.5μW,有效位数为11.2位,无杂散动态范围为75.6 dB。Digital-to-analog converter(DAC)was one of the main energy and area consumption sources in the successive approximation register analog-to-digital converter(SAR ADC).A low overhead capacitor switching scheme was proposed to reduce the area and energy consumption of DAC.The structure of DAC and the logic implementation process were described in detail.Compared with the conventional techniques,98.45%energy and 87.5%total capacitor area were saved in the proposed switching scheme.Based on this low overhead switching scheme,a 12-bit SAR ADC was realized.Simulation results showed that the power consumption was 12.5μW,the effective number of bit(ENOB)was 11.2 bit,and the spur-free dynamic range(SFDR)was 75.6 dB with the supply voltage of 1.2 V and the sampling rate of 100 kS/s.

关 键 词：逐次逼近型模数转换器 低开销 电容开关时序 逻辑实现 

分 类 号：TN792[电子电信—电路与系统]