FPGA的SDR/DDR3 SDRAM控制器设计  

Design of SDR/DDR3 SDRAM Controllers Based on FPGA

作　　者：潘亮 穆仕博[1] 何广亮 袁晓垒 Pan Liang;Mu Shibo;He Guangliang;Yuan Xiaolei(China Airborne Missile Academy Seventh Department,Luoyang 471009,China)

机构地区：[1]中国空空导弹研究院第七研究所

出　　处：《单片机与嵌入式系统应用》2020年第1期52-55,共4页Microcontrollers & Embedded Systems

摘　　要：本文在研究SDR存储机理和芯片内部操作的基础上,基于PCI总线和FPGA技术设计其接口控制器,并在Vivado 16.2软件环境中用VHDL编程实现,同时进一步根据课题需要梳理DDR3存储特点,开展DDR3控制器设计。针对联调中关键难题,如模式寄存器加载、数据流同步等,提出了解决办法。利用某PCI板卡和某型Xilinx评估板搭建了硬件测试平台并完成两型控制器的硬件测试。测试结果表明,所设计的控制器满足课题要求,具有一定工程应用价值。With the research of SDR storage mechanism and internal operation of the chip,a kind of interface controller based on the PCI bus and FPGA technology is proposed,which is implemented in Vivado 16.2 software environment with the VHDL.At the same time,the characteristics of DDR3 storage are sorted out and the design of DDR3 controller is carried out according to the needs of the subject.For the key problems in intermodulation,such as mode register loading and data stream synchronization,some solutions are proposed.With a PCI board and a Xilinx evaluation board,the hardware testing of the two controllers is completed on the built hardware testing platforms.The test results show that the designed controllers meet and have engineering application value.

关 键 词：SDR控制器 DDR3控制器 PCI总线 FPGA 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]