FPGA控制DDR2储存的光纤转换DIO板卡设计  

FPGA Controlling DDR2 Storage for Fiber Conversion DIO Board Design

作　　者：周舜民 毛瑞士[1] 杨海波[1] 赵祖龙[1] 赵铁成[1] 徐治国[1] 陈玉聪 李敏[1] ZHOU Shun-min;MAO Rui-shi;YANG Hai-bo;ZHAO Zu-long;ZHAO Tie-cheng;XU Zhi-guo;CHEN Yu-cong;LI Min(Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院近代物理研究所,甘肃兰州730000 [2]中国科学院大学,北京100049

出　　处：《仪表技术与传感器》2019年第12期31-34,44,共5页Instrument Technique and Sensor

基　　金：国家自然科学基金项目(Y862030GJ0)

摘　　要：文中设计了通过FPGA控制带有DDR2模块可实现大量数据存储功能的光纤收发型DIO板卡。设计中直接通过光纤收发模块收发光纤上传输的数据,对光纤收发模块和FPGA进行数据通信功能直接FIFO缓存传输和采用UART格式传输的两种方法进行介绍,对DDR2的PCB布线注意事项和时序进行分析。通过DDR2缓存可以很好地防止数据传输过快来不及处理而丢失。系统中对MCB进行二次封装,对DDR2用户接口控制实现采用非满即写、非空即读的方法,可以很好地实现MCB读取DDR2有效带宽最大化,也方便移植到其他DDR控制平台上实现。最后对整个系统进行硬件平台的验证。This paper introduced the implementation of fiber-optic transceiver DIO design that can realize a large amount of data storage function with DDR2 module through FPGA.In the design,the data transmitted on the optical fiber was directly transmitted or received through the optical transceiver module,introduced two methods of data communication between the optical transceiver module and FPGA,directly transmitted into the FIFO buffer and using the UART format transmission.PCB layout considerations and timing of DDR2 were analyzed.The DDR2 cache was a good way to prevent data from being lost too quickly to process.In this system,the MCB was secondarily packaged,and the DDR2 user interface control adopted method of non-full write,non-empty read,which can achieve the maximum effective bandwidth of MCB reading DDR2,and was convenient to transplant and implement on other DDR control platform.Finally,the entire system was verified on the hardware platform.

关 键 词：FPGA DDR2 光纤收发模块 UART MCB FIFO 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]