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作 者:武建平 徐浩[2] Wu Jianping;Xu Hao(Jiangsu YUNDONE Electronic Technology Co,Ltd,Nantong,226001;College of Electronics and OpticalEngineering,Nanjing University of Posts and Telecommunications,Nanjing,210046)
机构地区:[1]江苏云巅电子科技有限公司,南通226001 [2]南京邮电大学电子与光学工程学院,南京210046
出 处:《数字通信世界》2019年第12期73-75,共3页Digital Communication World
摘 要:提出了一款工作在近阈值电源电压环境下的数控振荡器,采用了桥接电容技术调制电容,提高频率分辨率,提出了电流复用结构,将NMOS和PMOS叠加成交叉耦合对,使同一电流从近阈值电源流入晶体管,电流重复利用,在低电压和较低电流条件下,大大降低电路功率。130nm工艺流片显示:0.6V低电压下,DCO总功耗为0.6mW。调制后单位可变电容约为2aF,频率分辨率约为3kHz/LSB。调频范围从2.4GHz到2.5GHz,对应相噪仿真为-134dBc/Hz@1MHz到-131dBc/Hz@1MHz。2.4GHz处锁相环带外相位噪声测试结果为-131dBc/Hz@1MHz,实现了低功耗和高性能要求。A designed Digital-Controlled Oscillator work under the near-threshold voltage environment,which adopts the bridge capacitance technology to reduce the capacitance and improve the frequency resolution.The current reuse structure is also adopted in the DCO.In order to reduce the power dissipation,a current-reuse structure under a 0.6V supply is used.By stacking a NMOS and a PMOS as crosscoupled pair,a same current from the near-threshold supply is fl owing into the transistors for current to be reused.Therefore,the power is greatly reduced due to both the lower current and lower supply.The proposed DCO was used in digital phase locked loop was fabricated in the 130-nm CMOS technology and worked at a 0.6V power supply.The total power consumption of the DCO was 0.6mW.The variable unit capacitance was 2aF after modulation,the frequency resolution is approximately 3kHz/LSB.The frequency range was from 2.4GHz to 2.5GHz,while the phase noise simulation was from-134dBc/Hz@1MHz offset to-131dBc/Hz@1MHz offset.At 2.4 GHz,the phase noise test result of the digital phase locked loop was about-131dBc/Hz@1MHz offset.
分 类 号:TN929.53[电子电信—通信与信息系统] TP309.2[电子电信—信息与通信工程]
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