用于高速模数转换器的电荷泵型低抖动时钟管理电路  

A Low Jitter Charge Pump Based Clock Management Circuit for High Speed Analog-to-Digital Converters

作　　者：李楠楠 黄正波 季惠才[2] 盛炜[2] 张鸿[1] LI Nannan;HUANG Zhengbo;JI Huicai;SHENG Wei;ZHANG Hong(School of Microelectronics,Xi’an Jiaotong University,Xi’an 710049,China;No.58 Research Institute,China Electronic Technology Group Corporation,Wuxi,Jiangsu 214000,China)

机构地区：[1]西安交通大学微电子学院,西安710049 [2]中国电子科技集团公司第五十八研究所,江苏无锡214000

出　　处：《西安交通大学学报》2020年第1期162-168,共7页Journal of Xi'an Jiaotong University

基　　金：国家自然科学基金资助项目(61974118);模拟集成电路重点实验室基金资助项目(6142802180105)

摘　　要：针对高速模数转换器(ADC)对时钟信号的占空比以及低抖动的要求,提出了一种电荷泵型的时钟管理电路,利用电荷泵构成两个闭环回路,分别实现占空比稳定和可调双相不交叠时钟产生功能。电荷泵对时钟相位的积分功能可实现宽范围的时钟占空比调节,并能明显抑制电源噪声对时钟下降沿抖动的影响。该时钟管理电路采用0.18μm标准CMOS工艺设计。版图寄生参数提取后的仿真结果表明:该时钟管理电路可在40~200 MHz频率范围内,将20%~80%的输入占空比稳定地调整到45%~55%的范围内;在200 mV电源干扰的条件下,输出时钟抖动可降低到传统RC型占空比稳定电路的1/10之下。将该时钟电路应用于一款双通道、200MSPS、14位的流水线ADC中,测试结果表明ADC的信号噪声失真比达到了73.01 dB。To fulfil the requirements of wide-range duty cycle adjustment and low jitter for the clock signals of high-speed analog-to-digital converters(ADC),a charge-pump type clock management circuit was proposed,which uses charge pumps to form two closed loops,achieving wide-range duty cycle stabilization and adjustable two-phase non-overlapping clock generation.The charge pump’s integral function of the clock phase extends the range of the input clock duty cycle stabilization and significantly suppresses the effect of power supply noise on the falling edge of the clock.Designed in a 0.18μm standard CMOS process,the post-layout simulation results showed that the input signal frequency range of the proposed clock management circuit is 40-200 MHz,and the clock duty cycle can be stably adjusted into the range of 45%-55%within an input duty cycle of 20%-80%.Under the condition of 200 mV power supply interference,the output clock jitter can be reduced by a factor of ten compared with the traditional RC-type duty cycle stabilization circuit at low frequency.The proposed clock circuit was applied to a dual-channel,200MSPS,14-bit pipeline ADC,and a signal-to-noise-to-distortion ratio of 73.01 dB is achieved.

关 键 词：流水线ADC 时钟管理电路 电荷泵 占空比稳定 

分 类 号：TN432[电子电信—微电子学与固体电子学]