HEVC帧内预测算法加速设计与实现  

ACCELERATION DESIGN AND IMPLEMENTATION OF HEVC INTRA PREDICTION ALGORITHM

作　　者：王飞龙 刘新闯 刘鹏 辛晓斐 石鹏飞 Wang Feilong;Liu Xinchuang;Liu Peng;Xin Xiaofei;Shi Pengfei(School of Electronic Engineering,Xi an University of Posts and Telecommunications,Xi an 710121,Shaanxi,China;School of Computer,Xi an University of Posts and Telecommunications,Xi an 710121,Shaanxi,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安邮电大学计算机学院,陕西西安710121

出　　处：《计算机应用与软件》2020年第1期151-156,共6页Computer Applications and Software

基　　金：国家自然科学基金项目(61772417,61602377,61634004,61272120);陕西省科技统筹创新工程项目(2016KTZDGY02-04-02);陕西省重点研发计划项目(2017GY-060)

摘　　要：新一代视频编码标准获得了较高的编码效率,但同时也增加了计算量。HEVC(High Efficiency Video Coding)并行算法能够提高编码速度,开发适用于多核处理器的并行编码算法对于满足高清视频实时传输和大规模实时共享具有十分重要的意义。分析帧内预测算法在处理像素过程中数据之间的依赖关系,进行基于预测模式的细粒度并行性的设计。块与块之间采用流水线处理,减少帧内预测算法的执行时间。利用动态可编程可重构视频阵列处理器,对帧内预测算法进行验证。实验结果表明,相比于HM16.0官方测试标准,信噪比提高了10%,算法的执行时间减少了大约70%。The new generation of video coding standards have achieved higher coding efficiency,but it increases the amount of computation.The HEVC(High Efficiency Video Coding)parallel algorithm can improve the encoding speed.Developing a parallel encoding algorithm suitable for multi-core processors is of great significance for real-time transmission of high-definition video and large-scale real-time sharing.The dependence of the intra prediction algorithm on the date in the process processing pixels was analyzed,and we designed fine-grained parallelism based on prediction mode.Pipelining was used between blocks to reduce the execution time of intra prediction algorithm.The intra prediction algorithm was verified by using a dynamically programmable reconfigurable video array processor.The experimental results show that compared with the HM16.0 official tests,the signal-to-noise ratio is increased by 10%,and the execution time of the algorithm is reduced by about 70%.

关 键 词：高效率视频编码 并行性 细粒度 帧内预测算法 阵列处理器 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术] TN919.81[电子电信—通信与信息系统]