一款低相位噪声的可编程分频器  

A Programmable Frequency Divider with Low Phase Noise

作　　者：王增双 高晓强 Wang Zengshuang;Gao Xiaoqiang({The 3th Research Institute,CETC,Shijiazhuang 050051,China)

机构地区：[1]中国电子科技集团公司第十三研究所

出　　处：《半导体技术》2019年第12期916-920,共5页Semiconductor Technology

摘　　要：设计了一款低相位噪声的可编程分频器,主要用于高鉴相频率的锁相环频率源中。电路设计采用2/3分频器级联结构,通过数选电路实现连续可变分频。从相位噪声产生机理、噪声来源及相位噪声与抖动的关系等方面分析影响分频器相位噪声的关键因素,通过工艺选择、电路设计和仿真分析来优化分频器的相位噪声。采用0.13μm SiGe BiCOMS工艺进行了设计仿真和流片,芯片面积为1.3 mm^2。测试结果表明:该分频器最高工作频率为20 GHz,电源电压为+3.3 V,最大电流为80 mA,可实现1~31连续分频,在输入6 GHz正弦波信号下20分频时的相位噪声为-145 dBc/Hz@1 kHz。A programmable frequency divider with low phase noise was designed,which is mainly used in phase-locked loop(PLL)frequency source with high phase detection frequency.A 2/3 frequency divider cascaded structure was adopted in the circuit of the programmable frequency divider.The continuous variable frequency division was realized through digital selective circuit.The key factors affecting the phase noise of the frequency divider were analyzed in terms of the generation mechanism of the phase noise,the noise source and the relationship between the phase noise and jitter.The phase noise of the frequency divider was optimized by the process selection,circuit design,and simulation analysis.The frequency divider chip with an area of 1.3 mm^2 was designed and fabricated using the 0.13μm SiGe BiCOMS process.The test results show that the maximum operating frequency is 20 GHz,the power supply voltage is+3.3 V,and the maximum current is 80 mA.The frequency divider can achieve 1~31 continuous frequency division.The phase noise of the 6 GHz input sinusoidal signal is-145 dBc/Hz@1 kHz at 20-frequency division.

关 键 词：低相位噪声 分频器 锁相环(PLL) SIGE BiCOMS工艺 

分 类 号：TN433[电子电信—微电子学与固体电子学]